Patents by Inventor Erich J. Plondke
Erich J. Plondke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10437591Abstract: An apparatus includes a first processor having a first instruction set and a second processor having a second instruction set that is different than the first instruction set. The apparatus also includes a memory storing at least a portion of an operating system. The operating system is concurrently executable on the first processor and the second processor.Type: GrantFiled: February 26, 2013Date of Patent: October 8, 2019Assignee: QUALCOMM IncorporatedInventors: Michael R. McDonald, Erich J. Plondke, Pavel Potoplyak, Lucian Codrescu, Richard Kuo, Bryan C. Bayerdorffer
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Patent number: 9785434Abstract: An apparatus, system and method of determining an extremum are disclosed. A reference location identifier and a reference extremum are coupled. An input extremum of an input data set is determined and a corresponding location identifier of the input extremum is also determined. The input extremum is compared with the reference extremum to determine an output extremum and output location identifier, based on the comparison.Type: GrantFiled: September 23, 2011Date of Patent: October 10, 2017Assignee: QUALCOMM IncorporatedInventors: Erich J. Plondke, Lucian Codrescu, Mao Zeng, Swaminathan Balasubramanian, David J. Hoyle
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Patent number: 9501332Abstract: An apparatus include a first core processor, a second core processor, and a lock register coupled to the first core processor and to the second core processor. The apparatus further includes a shared structure responsive to the first core processor and to the second core processor. The shared structure is responsive to an unlock instruction issued by either the first core processor or the second core processor to send a signal to the lock register to reset a lock indication in the lock register.Type: GrantFiled: December 20, 2012Date of Patent: November 22, 2016Assignee: QUALCOMM IncorporatedInventors: Dana M. Vantrease, Christopher E. Koob, Erich J. Plondke
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Patent number: 9208102Abstract: An apparatus includes a translation lookaside buffer (TLB). The TLB includes at least one entry that includes an entry virtual address and an entry page size indication corresponding to an entry page. The apparatus also includes input logic configured to receive an input page size indication and an input virtual address corresponding to an input page. The apparatus further includes overlap checking logic configured to determine, based at least in part on the entry page size indication and the input page size indication, whether the input page overlaps the entry page.Type: GrantFiled: January 15, 2013Date of Patent: December 8, 2015Assignee: Qualcomm IncorporatedInventors: Suresh K. Venkumahanti, Erich J. Plondke, Lucian Codrescu, Shane M. Mahon, Rahul R. Toley, Fadi A. Hamdan
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Patent number: 8843730Abstract: An apparatus includes a processor and a memory coupled to the processor. The memory stores an instruction packet (e.g., a VLIW instruction packet) including a first predicate independent instruction and a second predicate independent instruction. Each of the predicate independent instructions has the same destination.Type: GrantFiled: September 9, 2011Date of Patent: September 23, 2014Assignee: QUALCOMM IncorporatedInventors: Erich J. Plondke, Lucian Codrescu, Mao Zeng, Charles Joseph Tabony, Suresh K. Venkumahanti
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Publication number: 20140244983Abstract: An apparatus includes a first processor having a first instruction set and a second processor having a second instruction set that is different than the first instruction set. The apparatus also includes a memory storing at least a portion of an operating system. The operating system is concurrently executable on the first processor and the second processor.Type: ApplicationFiled: February 26, 2013Publication date: August 28, 2014Applicant: Qualcomm IncorporatedInventors: Michael R. McDonald, Erich J. Plondke, Pavel Potoplyak, Lucian Codrescu, Richard Kuo, Bryan C. Bayerdorffer
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Publication number: 20140201494Abstract: An apparatus includes a translation lookaside buffer (TLB). The TLB includes at least one entry that includes an entry virtual address and an entry page size indication corresponding to an entry page. The apparatus also includes input logic configured to receive an input page size indication and an input virtual address corresponding to an input page. The apparatus further includes overlap checking logic configured to determine, based at least in part on the entry page size indication and the input page size indication, whether the input page overlaps the entry page.Type: ApplicationFiled: January 15, 2013Publication date: July 17, 2014Applicant: Qualcomm IncorporatedInventors: Suresh K. Venkumahanti, Erich J. Plondke, Lucian Codrescu, Shane M. Mahon, Rahul R. Toley, Fadi A. Hamdan
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Publication number: 20140181341Abstract: An apparatus include a first core processor, a second core processor, and a lock register coupled to the first core processor and to the second core processor. The apparatus further includes a shared structure responsive to the first core processor and to the second core processor. The shared structure is responsive to an unlock instruction issued by either the first core processor or the second core processor to send a signal to the lock register to reset a lock indication in the lock register.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: QUALCOMM IncorporatedInventors: Dana M. Vantrease, Christopher E. Koob, Erich J. Plondke
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Patent number: 8756601Abstract: A system and method for memory coherency acceleration via virtual machine migration comprises a plurality of processors. A first processor of the plurality of processors is configured to implement at least one virtual machine. A monitor is configured to monitor a number of memory requests between the first processor and at least a second processor of the plurality of processors. A virtual machine manager is configured to migrate at least a portion of the virtual machine from the first processor to the second processor based on the number of memory requests exceeding a threshold.Type: GrantFiled: September 23, 2011Date of Patent: June 17, 2014Assignee: QUALCOMM IncorporatedInventors: Erich J. Plondke, Lucian Codrescu
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Patent number: 8479207Abstract: A method includes determining that a first task having a first priority is blocked from execution at a multithreaded processor by a second task having a second priority that is lower than the first priority. A temporary priority of the second task is set to be equal to an elevated priority, such that in response to the second task being preempted from execution by another task, the second task is rescheduled for execution based on the elevated priority identified by the temporary priority.Type: GrantFiled: February 25, 2011Date of Patent: July 2, 2013Assignee: QUALCOMM IncorporatedInventor: Erich J. Plondke
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Publication number: 20130080738Abstract: In a particular embodiment, a very long instruction word (VLIW) processor is operable to execute VLIW instructions. At least one of the VLIW instructions includes a first load or store instruction and a second load or store instruction. The first instruction and the second instruction are executed as a single atomic unit. At least one of the first and second instructions is a store-conditional instruction.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Applicant: QUALCOMM INCORPORATEDInventors: Erich J. Plondke, Ajay A. Ingle, Lucian Codrescu
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Publication number: 20130080490Abstract: An apparatus, system and method of determining an extremum are disclosed. A reference location identifier and a reference extremum are coupled. An input extremum of an input data set is determined and a corresponding location identifier of the input extremum is also determined. The input extremum is compared with the reference extremum to determine an output extremum and output location identifier, based on the comparison.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Applicant: QUALCOMM INCORPORATEDInventors: Erich J. Plondke, Lucian Codrescu, Mao Zeng, Swaminathan Balasubramanian, David J. Hoyle
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Publication number: 20130081013Abstract: A system and method for memory coherency acceleration via virtual machine migration comprises a plurality of processors. A first processor of the plurality of processors is configured to implement at least one virtual machine. A monitor is configured to monitor a number of memory requests between the first processor and at least a second processor of the plurality of processors. A virtual machine manager is configured to migrate at least a portion of the virtual machine from the first processor to the second processor based on the number of memory requests exceeding a threshold.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Applicant: QUALCOMM INCORPORATEDInventors: Erich J. Plondke, Lucian Codrescu
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Publication number: 20130067205Abstract: An apparatus includes a processor and a memory coupled to the processor. The memory stores an instruction packet (e.g., a VLIW instruction packet) including a first predicate independent instruction and a second predicate independent instruction. Each of the predicate independent instructions has the same destination.Type: ApplicationFiled: September 9, 2011Publication date: March 14, 2013Applicant: QUALCOMM IncorporatedInventors: Erich J. Plondke, Lucian Codrescu, Mao Zeng, Charles J. Tabony, Suresh K. Venkumahanti
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Publication number: 20120222035Abstract: A method includes determining that a first task having a first priority is blocked from execution at a multithreaded processor by a second task having a second priority that is lower than the first priority. A temporary priority of the second task is set to be equal to an elevated priority, such that in response to the second task being preempted from execution by another task, the second task is rescheduled for execution based on the elevated priority identified by the temporary priority.Type: ApplicationFiled: February 25, 2011Publication date: August 30, 2012Applicant: QUALCOMM IncorporatedInventor: Erich J. Plondke
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Patent number: 8190854Abstract: A method of processing data is disclosed that includes performing a fetch of a plurality of instructions from a memory unit. The method also includes grouping the plurality of instructions into packets of instructions of different types for parallel execution by a plurality of instruction execution units. The packets of instructions include a first instruction and a second instruction. The method includes using a combined scalar and vector condition code register to execute the first instruction for a compare operation and the second instruction for a conditional operation using the combined scalar and vector condition code register. The method also includes when the compare operation is a scalar compare operation, receiving a scalar compare instruction for the scalar compare operation at an instruction executing unit and storing results of the scalar compare operation in the combined scalar and vector condition code register.Type: GrantFiled: January 20, 2010Date of Patent: May 29, 2012Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, Erich J. Plondke, Taylor Simpson
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Publication number: 20100118852Abstract: A method of processing data is disclosed that includes performing a fetch of a plurality of instructions from a memory unit. The method also includes grouping the plurality of instructions into packets of instructions of different types for parallel execution by a plurality of instruction execution units. The packets of instructions include a first instruction and a second instruction. The method includes using a combined scalar and vector condition code register to execute the first instruction for a compare operation and the second instruction for a conditional operation using the combined scalar and vector condition code register. The method also includes when the compare operation is a scalar compare operation, receiving a scalar compare instruction for the scalar compare operation at an instruction executing unit and storing results of the scalar compare operation in the combined scalar and vector condition code register.Type: ApplicationFiled: January 20, 2010Publication date: May 13, 2010Applicant: QUALCOMM INCORPORATEDInventors: Lucian Codrescu, Erich J. Plondke, Taylor Simpson