Patents by Inventor Erich James Plondke
Erich James Plondke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8601234Abstract: The disclosure includes a method and system of configuring a translation lookaside buffer (TLB). In an embodiment, the TLB includes a first portion and a second portion. The first portion or the second portion may be selectively disabled in response to a value of a TLB configuration indicator.Type: GrantFiled: November 7, 2007Date of Patent: December 3, 2013Assignee: QUALCOMM IncorporatedInventors: Erich James Plondke, Ajay Anant Ingle, Lucian Codrescu, Paul Bassett
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Publication number: 20130254489Abstract: A computer readable storage medium includes instructions that, when executed by a processor, cause the processor to receive an index value included in a cache invalidate by index instruction, an encoded way value, and an incrementer output value. The instructions further cause the processor to assign the index value as an identifier value in response to receiving the cache invalidate by index instruction. The identifier value indicates a cache line for replacement.Type: ApplicationFiled: May 15, 2013Publication date: September 26, 2013Applicant: QUALCOMM IncorporatedInventors: Ajay Anant Ingle, Erich James Plondke, Lucian Codrescu
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Publication number: 20130212357Abstract: Systems and methods for generating a floating point constant value from an instruction are disclosed. A first field of the instruction is decoded as a sign bit of the floating point constant value. A second field of the instruction is decoded to correspond to an exponent value of the floating point constant value. A third field of the instruction is decoded to correspond to the significand of the floating point constant value. The first field, the second field, and the third field are combined to form the floating point constant value. The exponent value may include a bias, and a bias constant may be added to the exponent value to compensate for the bias. The third field may comprise the most significant bits of the significand. Optionally, the second field and the third field may be shifted by first and second shift values respectively before they are combined to form the floating point constant value.Type: ApplicationFiled: February 9, 2012Publication date: August 15, 2013Applicant: QUALCOMM INCORPORATEDInventors: Erich James Plondke, Lucian Codrescu, Charles Joseph Tabony, Swaminathan Balasubramanian
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Publication number: 20130179642Abstract: Systems and methods for performing non-allocating memory access instructions with physical address. A system includes a processor, one or more levels of caches, a memory, a translation look-aside buffer (TLB), and a memory access instruction specifying a memory access by the processor and an associated physical address. Execution logic is configured to bypass the TLB for the memory access instruction and perform the memory access with the physical address, while avoiding allocation of one or more intermediate levels of caches where a miss may be encountered.Type: ApplicationFiled: February 17, 2012Publication date: July 11, 2013Applicant: QUALCOMM INCORPORATEDInventors: Erich James Plondke, Ajay Anant Ingle, Lucian Codrescu
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Patent number: 8464000Abstract: A system for determining a cache line to replace is described. In one embodiment, the system includes a cache comprising a plurality of cache lines. The system further includes an identifier configured to identify a cache line for replacement. The system also includes a control logic configured to determine a value of the identifier selected from an incrementer, a cache maintenance instruction, or remains the same.Type: GrantFiled: February 29, 2008Date of Patent: June 11, 2013Assignee: QUALCOMM IncorporatedInventors: Ajay Anant Ingle, Erich James Plondke, Lucian Codrescu
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Patent number: 8429378Abstract: A system and method to manage a translation lookaside buffer (TLB) is disclosed. In a particular embodiment, a method of managing a first TLB includes in response to starting execution of a memory instruction, setting a first field associated with an entry of the first TLB to indicate use of the entry. The method also includes setting a second field to indicate that the entry in the first TLB matches a corresponding entry in a second TLB.Type: GrantFiled: July 6, 2010Date of Patent: April 23, 2013Assignee: QUALCOMM IncorporatedInventors: Ajay Anant Ingle, Erich James Plondke, Muhammad T. Rab
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Publication number: 20130086290Abstract: Systems and method for reducing interrupt latency time in a multi-threaded processor. A first interrupt controller is coupled to the multi-threaded processor. A second interrupt controller is configured to communicate a first interrupt and a first vector identifier to the first interrupt controller, wherein the first interrupt controller is configured to process the first interrupt and the first vector identifier and send the processed interrupt to a thread in the multi-threaded processor. Logic is configured to determine when the multi-threaded processor is ready to receive a second interrupt. A dedicated line is used to communicate an indication to the second interrupt controller that the multi-threaded processor is ready to receive the second interrupt.Type: ApplicationFiled: October 4, 2011Publication date: April 4, 2013Applicant: QUALCOMM INCORPORATEDInventors: Suresh K. Venkumahanti, Lucian Codrescu, Erich James Plondke, Xufeng Chen, Peixin Zhong
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Publication number: 20130086360Abstract: An instruction identifies a register and a memory location. Upon execution of the instruction by a processor, an item is loaded from the memory location and a shift and insert operation is performed to shift data in the register and to insert the item into the register.Type: ApplicationFiled: September 30, 2011Publication date: April 4, 2013Applicant: QUALCOMM INCORPORATEDInventors: Mao Zeng, Lucian Codrescu, Erich James Plondke, Ajay Anant Ingle
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Publication number: 20130061020Abstract: A method includes selectively routing a physical address to an originating device instead of to a shared memory at controller that manages conversion of device virtual addresses to physical addresses. The physical address corresponds to a data access from a virtual device. The method may provide local coherency at a computing system that implements virtualized input/output.Type: ApplicationFiled: September 1, 2011Publication date: March 7, 2013Applicant: QUALCOMM INCORPORATEDInventors: Christopher Edward Koob, Lucian Codrescu, Erich James Plondke, Bryan C. Bayerdorffer
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Publication number: 20130042091Abstract: An instruction specifies a source value and an offset value. Upon execution of the instruction, a first result of the instruction and a second result of the instruction are generated. The first result is a first portion of the source value and the second result is a second portion of the source value.Type: ApplicationFiled: August 12, 2011Publication date: February 14, 2013Applicant: QUALCOMM INCORPORATEDInventors: Mao Zeng, Lucian Codrescu, Erich James Plondke
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Publication number: 20130024663Abstract: An apparatus includes a memory that stores an instruction including an opcode and an operand. The operand specifies an immediate value or a register indicator of a register storing the immediate value. The immediate value is usable to identify a function call address. The function call address is selectable from a plurality of function call addresses.Type: ApplicationFiled: July 19, 2011Publication date: January 24, 2013Applicant: QUALCOMM INCORPORATEDInventors: Erich James Plondke, Lucian Codrescu, Charles Joseph Tabony, Ajay Anant Ingle, Suresh K. Venkumahanti, Evandro Carlos Menezes
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Publication number: 20120297256Abstract: Systems and method for configuring a page-based memory device without pre-existing dedicated metadata. The method includes reading metadata from a metadata portion of a page of the memory device, and determining a characteristic of the page based on the metadata. The memory device may be configured as a cache. The metadata may include address tags, such that determining the characteristic may include determining if desired information is present in the page, and reading the desired information if it is determined to be present in the page. The metadata may also include error-correcting code (ECC), such that determining the characteristic may include detecting errors present in data stored in the page. The metadata may further include directory information, memory coherency information, or dirty/valid/lock information.Type: ApplicationFiled: May 20, 2011Publication date: November 22, 2012Applicant: QUALCOMM INCORPORATEDInventors: Erich James Plondke, Lucian Codrescu, William C. Anderson
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Publication number: 20120284489Abstract: Programs often require constants that cannot be encoded in a native instruction format, such as 32-bits. To provide an extended constant, an instruction packet is formed with constant extender information and a target instruction. The constant extender information encoded as a constant extender instruction provides a first set of constant bits, such as 26-bits for example, and the target instruction provides a second set of constant bits, such as 6-bits. The first set of constant bits are combined with the second set of constant bits to generate an extended constant for execution of the target instruction. The extended constant may be used as an extended source operand, an extended address for memory access instructions, an extended address for branch type of instructions, and the like. Multiple constant extender instructions may be used together to provide larger constants than can be provided by a single extension instruction.Type: ApplicationFiled: June 8, 2011Publication date: November 8, 2012Applicant: QUALCOMM INCORPORATEDInventors: Erich James Plondke, Lucian Codrescu, Charles Joseph Tabony, Suresh K. Venkumahanti, Ajay Anant Ingle
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Publication number: 20120284488Abstract: Programs often require constants that cannot be encoded in a native instruction format, such as 32-bits. To provide an extended constant, an instruction packet is formed with constant extender information and a target instruction. The constant extender information encoded as a constant extender instruction provides a first set of constant bits, such as 26-bits for example, and the target instruction provides a second set of constant bits, such as 6-bits. The first set of constant bits are combined with the second set of constant bits to generate an extended constant for execution of the target instruction. The extended constant may be used as an extended source operand, an extended address for memory access instructions, an extended address for branch type of instructions, and the like. Multiple constant extender instructions may be used together to provide larger constants than can be provided by a single extension instruction.Type: ApplicationFiled: May 3, 2011Publication date: November 8, 2012Applicant: QUALCOMM INCORPORATEDInventors: Erich James Plondke, Lucian Codrescu, Charles Joseph Tabony, Suresh K. Venkumahanti, Ajay Anant Ingle
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Patent number: 8260990Abstract: A system and method for selective preclusion of bus access requests are disclosed. In an embodiment, a method includes determining a bus unit access setting at a logic circuit of a processor. The method also includes selectively precluding a bus unit access request based on the bus unit access setting.Type: GrantFiled: November 19, 2007Date of Patent: September 4, 2012Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, Ajay Anant Ingle, Christopher Edward Koob, Erich James Plondke
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Patent number: 8250332Abstract: In a particular embodiment, a circuit device includes a translation look-aside buffer (TLB) configured to receive a virtual address and to translate the virtual address to a physical address of a cache having at least two partitions. The circuit device also includes a control logic circuit adapted to identify a partition replacement policy associated with the identified one of the at least two partitions based on a partition indicator. The control logic circuit controls replacement of data within the cache according to the identified partition replacement policy in response to a cache miss event.Type: GrantFiled: June 11, 2009Date of Patent: August 21, 2012Assignee: QUALCOMM IncorporatedInventors: Erich James Plondke, Lucian Codrescu, Ajay Ingle
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Patent number: 8243100Abstract: Systems and methods to perform fast rotation operations are disclosed. In a particular embodiment, a method includes executing a single instruction. The method includes receiving first data indicating a first coordinate and a second coordinate, receiving a first control value that indicates a first rotation value selected from a set of ninety degree multiples, and writing output data corresponding to the first data rotated by the first rotation value.Type: GrantFiled: June 26, 2008Date of Patent: August 14, 2012Assignee: QUALCOMM IncorporatedInventors: Shankar Krithivasan, Erich James Plondke, Lucian Codrescu, Mao Zeng, Remi Jonathan Gurski
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Patent number: 8185721Abstract: A system including a dual function adder is described. In one embodiment, the system includes an adder. The adder is configured for a first instruction to determine an address for a hardware prefetch if the first instruction is a hardware prefetch instruction. The adder is further configured for the first instruction to determine a value from an arithmetic operation if the first instruction is an arithmetic operation instruction.Type: GrantFiled: March 4, 2008Date of Patent: May 22, 2012Assignee: QUALCOMM IncorporatedInventors: Ajay Anant Ingle, Erich James Plondke, Lucian Codrescu
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Patent number: 8140823Abstract: Systems and methods including a multithreaded processor with a lock indicator are disclosed. In an embodiment, a system includes means for indicating a lock status of a shared resource in a multithreaded processor. The system includes means for automatically locking the shared resource before processing exception handling instructions associated with the shared resource. The system further includes means for unlocking the shared resource.Type: GrantFiled: December 3, 2007Date of Patent: March 20, 2012Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, Erich James Plondke, Suresh Venkumahanti
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Publication number: 20120011342Abstract: A system and method to manage a translation lookaside buffer (TLB) is disclosed. In a particular embodiment, a method of managing a first TLB includes in response to starting execution of a memory instruction, setting a first field associated with an entry of the first TLB to indicate use of the entry. The method also includes setting a second field to indicate that the entry in the first TLB matches a corresponding entry in a second TLB.Type: ApplicationFiled: July 6, 2010Publication date: January 12, 2012Applicant: QUALCOMM INCORPORATEDInventors: Ajay Anant Ingle, Erich James Plondke, Muhammad T. Rab