Abstract: Described is a novel implementation of a medium and high frequency on-module (off-chip)/on-chip power noise filter for power noise sensitive circuits. To achieve this, a second order low-pass approach is used. The first stage capacitor is located on-module (off-chip), and the second stage capacitor is implemented on-chip.

Abstract: An improved wiring structure to minimize coupling between the wiring in one metalization layer of an integrated circuit chip and the wiring in an adjoining metalization layer is described. Wiring in one layer is rotated by an angle a.sub.1 with respect to the direction of the wiring in the adjoining layer. By successively rotating all the conductors of one wiring layer with respect to the wiring of the next layer, the capacitive and inductive coupling between conductors in the various layers is minimized, thereby improving the overall high-frequency performance of the chip.

Abstract: The invention relates to a method for reducing a transient thermal mismatch between a first component and a second component which are in mechanical contact with one another. The temperature of the first component is controlled by the amount of energy dissipated thereby. The amount of energy dissipated is controlled as a function of a data pattern input into the first component which causes a certain number of gates within the component to switch per clock cycle. By determining the desired energy dissipation in terms of the number of gates which are to be switched and arranging the input data pattern accordingly, the thermal mismatch between the components may be reduced.

Abstract: The invention relates to a multilayer module 20 for packaging of at least one electronic component, such as the integrated circuit chips 21, 22. The module 20 comprises a thickfilm structure and a thinfilm structure. The thinfilm structure provides an interface between the electronic components and the thickfilm structure. The thinfilm structure comprises a first powerplane and a redistribution wiring structure. The topmost layer of conductors of the thickfilm structure is a second powerplane so that an electrical structure approaching a triplate structure is realized.

Abstract: A multilayer module for packaging at least one electronic component 50. The module includes a plurality of thickfilm layers, and a wiring structure 45 to permit the connection of on-module capacitors. The multilayer module is fabricated such that the wiring structure includes a partial mesh plane 46, 47, 48, and 49 between the topmost and second topmost layers of the thickfilm. Logic noise is reduced in the multilayer module by maximizing the mutual inductance between adjacent mesh planes.

Abstract: The semiconductor memory module comprises a housing of plastic or ceramic in which two chips are stacked together back-to-back. The pads of the chips are electrically connected by wire bonding to beam leads which comprise outer bond leads, generally arranged outside the housing to form the contact pins or contact leads of the module to a printed circuit board, and inner bond leads in the housing. The inner bond leads are split and spread in the area of the inner lead bond ends into upper and lower sets forming a gap for receiving and holding the stacked chips.

Abstract: Integrated circuit package comprising a power supply distribution wiring and a chip interconnection signal wiring both formed on the top surface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented.Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type.The power supply distribution wiring comprises first and second conductive lines (5,6) within a first wiring level (WL1).Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship.Said first and second conductive lines are connected to first and second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor.

Abstract: A semiconductor packaging subassembly is described in which a plurality of modules or chips, repsonsive to a plurality of common input signals, are provided with input signal redriver circuits. Each redriver circuit is responsive to an input and provides an output signal to each the of chips in the subassembly. The preferred embodiment is directed to a multi-module memory arrangement in which input signals including CAS, RAS, W and address signals are received and redriven.

Abstract: Integrated circuit package comprising a power supply distribution wiring and a chip interconnection signal wiring both formed on the top surface of a passive semiconductor interconnection carrier (2) in which a power supply decoupling capacitor is implemented.Spaced wells (4) of a first conductivity type are provided in the surface of said carrier of a second conductivity type.The power supply distribution wiring comprises first and second conductive lines (5,6) within a first wiring level (WL1).Said first conductive lines (5) are deposited on the surface areas of said wells (4) in an ohmic contact relationship and said second conductive lines (6) are deposited on the surface areas of said carrier (2) between said wells (4) in an ohmic contact relationship.Said first and second conductive lines are connected to first second terminals of the power supply, respectively, so that the junction capacitance between said wells (4) and the carrier material (2) embedding said wells forms said decoupling capacitor.

Abstract: A phase splitter with latch comprises a true complement generator in the form of a current switch (T1, T2, T3, R3) which supplies two complementary output signals in response to an input signal (VIN). The outputs of this true complement generator are in each case connected to an associated emitter follower (T4, T5). The two emitter followers (T4, T5) have identical emitter resistors (R6, R7) which simultaneously serve as collector load resistors of two cross-coupled transistors (T6, T7) also comprise identical but higher emitter resistors (R13, R14) than the emitter followers (T6, T7). The emitters of the cross-coupled transistors (T6, T7) are each connected to one of the two inputs of an output stage (T8, T9, T11) consisting of a current switch. This current switch is connected to operating voltage (VEE) through a clock-controlled transistor (T11). Upon actuation of the output stage, i.e.

Abstract: Disclosed is a phase splitter with integrated latch circuit, where the complementary output signals generated after an input signal applied to a true-complement generator are available directly without any load by the latch circuit, where upon a premature change of the input signal there is no undesired change of the previously set switching state or of the output signals, respectively, and where a simple clocking for functional control can be used. The advantages presented by the disclosed Phase splitter substantially consist in that the speed with which the complementary output signals are supplied is extremely high since the output signals are available directly, i.e. with only one stage delay, the latch circuit being non-conductive in the stationary state, and thus in a latching process does not have to be switched from one stage to the other, but only switched on.

Abstract: Semiconductor storage in which the current necessary for reading and/or writing the storage cells is generated simply by discharging input capacitances of the non-selected storage cells and is fed directly to the selected storage cells for reading and/or writing.

Abstract: Disclosed is a simulated storage cell structure for use as a reference voltage generator in a semiconductor store fabricated in Merged Transistor Logic (MTL) technology. The simulated storage cell structure includes n elongated regions of P-type diffusion arranged in parallel to each other in an N-type trough of semiconductor material. The elongated P-type regions are alternately designed as collector and Injector strips.

Abstract: The invention relates to a monolithically integrated semiconductor arrangement with at least one integrated injection logic (I.sup.2 L) structure including an injection zone and an inverting transistor, the injection zone, and lateral thereto, the transistor base zone of a same first conductivity type being arranged in a semiconductor layer of a second conductivity type, which forms the emitter zone of the transistor, the transistor being completed by a collector zone of the second conductivity type, which is formed in the base zone, and the I.sup.2 L structure being surrounded at least partly by a separating zone introduced at a predetermined spacing into the semiconductor layer. The injection zone and the transistor base zone in the region of their edges facing each other are extended up to or into the separating zone, while in the region of their remaining edges they are spaced therefrom at the predetermined distance.

Abstract: In an integrated circuit an improved highly integrated semiconductor structure for providing a Schottky diode-resistor circuit configuration is disclosed. Although not limited thereto, the improved highly integrated semiconductor structure has particular utility when employed in a monolithic memory.