Abstract: An integrated circuit includes a radio receiver for receiving a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies. The radio receiver converts a selected one of the plurality of channel signals into a demodulated signal. An interface clock generator generates a first interface clock at a first interface clock frequency that varies based on the selected one of the plurality of channel signals. The first interface clock frequency, and integer multiples of the first clock frequency are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals. A driver module drives a device interface with a device based on the first interface clock.

Abstract: A system on a chip integrated circuit includes a first digital module and a second digital module such that the second digital module generates an output during the predetermined period that is based on an output of the first digital module generated during a prior predetermined period. A digital clock generator generates a base clock signal having a plurality of first digital clock cycles over a predetermined period and a second digital clock signal having a plurality of second digital clock cycles over the predetermined period. The plurality of first digital clock cycles are substantially interleaved with the plurality of second digital clock cycles over the predetermined period.

Abstract: A system on a chip integrated circuit includes a first in-phase digital submodule and a first quadrature phase digital submodule such that the first in-phase digital submodule and the first quadrature phase digital submodule are operable to produce at least one output signal based on at least one input signal. A digital clock generator generates a first in-phase digital clock signal having a plurality of first in-phase digital clock cycles over a predetermined period and a first quadrature phase digital clock signal having a plurality of first quadrature phase digital clock cycles over the predetermined period. The plurality of first in-phase digital clock cycles are substantially interleaved with the plurality of first quadrature phase digital clock cycles over the predetermined period.

Abstract: A system on a chip integrated circuit includes an analog front end for receiving a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies, and for converting a selected one of the plurality of channel signals into a digital signal. A digital clock generator generates a digital clock signal at a digital clock frequency that varies based on the selected one of the plurality of channel signals. The digital clock frequency, and integer multiples of the digital clock frequency, are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals. A digital section converts the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channels, based on the digital clock signal.

Abstract: A digital clock generator includes a base clock generator for generating a base clock signal at a variable base clock frequency in response to a control signal. A digital clock controller generates a digital clock signal having a substantially constant number of digital clock cycles over a predetermined period.

Abstract: A system on a chip integrated circuit includes a first digital module a second digital module such that the first digital module and the second digital module are operably coupled to generate an output signal based on an input signal, based on the first digital clock signal and the second digital clock signal. A digital clock generator generates a base clock signal at a base clock frequency that varies based on a control signal and generates a first digital clock signal having a substantially constant number of first digital clock cycles over a predetermined period and for generating a second digital clock signal having a substantially constant number of second digital clock cycles over the predetermined period.

Abstract: A system on a chip integrated circuit includes a first circuit module and N other circuit modules that are operable to produce at least one output signal based on at least one input signal. A reference oscillator for generating a base clock signal for the first circuit module. A clock delay generator generates N delayed clock signals at a corresponding N clock delays, wherein N is greater than or equal to 2. The N delayed clock signals are provided to the N other circuit modules.

Abstract: A digital clock generator includes a base clock generator for generating a base clock signal at a variable base clock frequency in response to a control signal. A digital clock controller generates a digital clock signal having a substantially constant number of digital clock cycles over a predetermined period.

Abstract: An integrated circuit includes a radio receiver for receiving a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies. The radio receiver converts a selected one of the plurality of channel signals into a demodulated signal. An interface clock generator generates a first interface clock at a first interface clock frequency that varies based on the selected one of the plurality of channel signals. The first interface clock frequency, and integer multiples of the first clock frequency are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals. A driver module drives a device interface with a device based on the first interface clock.

Abstract: A system on a chip integrated circuit includes an analog front end for receiving a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies, and for converting a selected one of the plurality of channel signals into a digital signal. A digital clock generator generates a digital clock signal at a digital clock frequency that varies based on the selected one of the plurality of channel signals. The digital clock frequency, and integer multiples of the digital clock frequency, are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals. A digital section converts the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channels, based on the digital clock signal.

Abstract: A system on a chip integrated circuit includes a first in-phase digital submodule and a first quadrature phase digital submodule such that the first in-phase digital submodule and the first quadrature phase digital submodule are operable to produce at least one output signal based on at least one input signal. A digital clock generator generates a first in-phase digital clock signal having a plurality of first in-phase digital clock cycles over a predetermined period and a first quadrature phase digital clock signal having a plurality of first quadrature phase digital clock cycles over the predetermined period. The plurality of first in-phase digital clock cycles are substantially interleaved with the plurality of first quadrature phase digital clock cycles over the predetermined period.

Abstract: A system on a chip integrated circuit includes a first digital module a second digital module such that the first digital module and the second digital module are operably coupled to generate an output signal based on an input signal, based on the first digital clock signal and the second digital clock signal. A digital clock generator generates a base clock signal at a base clock frequency that varies based on a control signal and generates a first digital clock signal having a substantially constant number of first digital clock cycles over a predetermined period and for generating a second digital clock signal having a substantially constant number of second digital clock cycles over the predetermined period.

Abstract: A system on a chip integrated circuit includes a first circuit module and N other circuit modules that are operable to produce at least one output signal based on at least one input signal. A reference oscillator for generating a base clock signal for the first circuit module. A clock delay generator generates N delayed clock signals at a corresponding N clock delays, wherein N is greater than or equal to 2. The N delayed clock signals are provided to the N other circuit modules.

Abstract: A system on a chip integrated circuit includes a first digital module and a second digital module such that the second digital module generates an output during the predetermined period that is based on an output of the first digital module generated during a prior predetermined period. A digital clock generator generates a base clock signal having a plurality of first digital clock cycles over a predetermined period and a second digital clock signal having a plurality of second digital clock cycles over the predetermined period.