Patents by Inventor Erich P. ZWYSSIG

Erich P. ZWYSSIG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154592
    Abstract: An integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage, wherein the gain update circuitry comprises level detection circuitry configured to determine a signal level of the first input signal or the first output signal.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 9, 2024
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Andrew J. HOWLETT, Michael CHANDLER-PAGE, David P. SINGLETON, Erich P. ZWYSSIG, Craig MCADAM
  • Publication number: 20230353111
    Abstract: An integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage.
    Type: Application
    Filed: November 8, 2022
    Publication date: November 2, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Andrew J. HOWLETT, Michael CHANDLER-PAGE, David P. SINGLETON, Erich P. ZWYSSIG