Abstract: A film-mounted circuit includes a support film, metallic conductor runs formed of solderable material disposed on the support film, the conductor runs each having two ends, a contact area containing solder material electroplated on one of the ends and external terminal contacts containing solder material electroplated on the other of the ends for receiving a solder connection to external wiring, and a metallic semiconductor chip having hump-like terminal contacts each having a side with a surface area soldered to a respective one of the contact areas, the terminal contacts being formed of solderable material at least at the surface area thereof, the solderable material of the surface area of the terminal contacts forming an alloy together with the solder material of the contact areas deposited by electroplating during soldering, the alloy having an alloy ratio defined by a eutectic point, the melting point temperature of which is at least 20.degree. C.

Abstract: A semiconductor component having bump-like, metallic lead contacts and multilayer wiring wherein individual tracks of each and every electrical signal or potential to be wired in multilayer wiring technology are electrically connected to the respective lead contact in the region thereof and to one another, but are separated from one another in the remaining regions of the semiconductor component by insulating layers. The various insulating layers terminate at different distances from the lead contacts in such fashion that their ends, depending upon the embodiment, form a funnel that tapers either down or up. The difference of the respective distance of the ends of two neighboring insulating layers from the corresponding lead contacts amounts to at least twice the thickness of one of the two layers. Given different layer thicknesses, a dimension of the thicker layer is used. An insulating layer may be at most 2 .mu.m thick, and preferably 1 .mu.m.

Abstract: A method of galvanic manufacture of bump-like lead contacts of semiconductor components. The lead contacts are formed of etchable metals having a surface coating of gold. The gold is chemically deposited onto the lead contacts in a first and in a second work step. In the first work step, the deposition occurs to a thickness of 10 to 200 nm, and in the second work step to a thickness of 50 to 200 nm. Etching processes and a tempering occur between the two work steps. The surface layer applied in the first work step is employed during the etching processes as an etching mask for the lead contacts. This surface layer then diffuses into the lead contacts during the tempering. The solderablity of the lead contacts is thus preserved over a longer than usual time span (factor of 20).

Abstract: Electrically insulating encapsulating composition for semiconductor arrangements, consisting of a mixture of a resin and an inorganic filler, characterized by the feature that the filler is a silicon compound prepared from at least one highly volatile silicon halogenide compound, selected from the group of silicon oxides, silicon oxide hydrates and silicon nitrides. The filler may be aluminum oxide or aluminum hydroxide prepared from a volatile aluminum halogenide compound.

Abstract: Fast surface states in MOS devices, such as SCCDs, are reduced by depositing a relatively thin amorphous layer containing silicon and hydrogen onto the SiO.sub.2 surface of such devices and annealing the resultant device in a non-oxidizing atmosphere for brief periods of time at a temperature in excess of the deposition temperature for the amorphous layer but below about 500.degree. C. so that free valences at the Si-SiO.sub.2 interface region are saturated with hydrogen. Surface state densities of about 4.times.10.sup.8 cm.sup.-2 eV.sup.-1 and SCCDs having .epsilon.=1.10.sup.-5 can be achieved via this process. The process is useful in producing SCCDs with low surface state densities and other MOS devices having low surface generated dark currents.

Abstract: A semiconductor body having metal contacts is coated, except for the metal contacts, with a masking layer composed of a heat-resistant photo-lacquer or a polyimide resin which remains on the semi-conductor body as a protective layer on the finished semiconductor device. An intermediate metal coating consisting of at least two layers of different metals is vapor-deposited over the entire semiconductor body surface. The outer layer of metal is a soft-solderable metal, such as Cu, and is applied substantially thicker in relation to the underlying intermediate metal layers. Thereafter, any excess metal on the masking layer is removed therefrom by conventional etching techniques.

Abstract: Semiconductor structures and a method of producing the same comprising coating the surface of a semiconductor body with a first inorganic insulating layer; coating an electrical conductor path on the first insulating layer; coating an organic layer which includes a compatible compound therein which vaporizes at a relatively low temperature onto select points or portions of the conductor path; coating a second inorganic insulating layer on all exposed surfaces of the conductor path, the organic layer and the first insulating layer; and heating the resulting structure to a temperature sufficient to vaporize the compatible compound within the organic layer and remove areas of the second insulating layer which superimposed the organic layer so as to unmask the select portions of the conductor path for access to external electrical connection means.