Abstract: A processing circuit including a first multiplier to multiply least significant portions of a first and a second operand, a second multiplier to multiply a sum of a most and the least significant portion of the first operand with the sum of a most and the least significant portion of the second operand and the least significant portion of the second operand, a third multiplier to multiply the most significant portions of the first and the second operand and an output circuit to determine an output sum including the result of the first multiplier, the result of the third multiplier times two to the power of two times the bit number of the least significant portions, and, if enabled, the result of the second multiplier minus the results of the first and the third multiplier, times two to the power of the bit number of the least significant portions.

Abstract: According to various embodiments, a circuit for a combined key value-dependent exchange and randomization of two values is described comprising a control input circuit configured to supply two or more shares of a key to an exchange and randomizing circuit, wherein the exchange and randomizing circuit is configured to supply each of the two values to one of two inputs, wherein it depends on at least a first share of the shares which value of the two values is supplied to which input of the two inputs, arithmetically combine, for each of the two inputs, the value supplied to the input with a randomization value to generate a respective randomized value and to store the randomized values in two result locations, wherein it depends on at least a second share of the shares which randomized value is stored into which result location of the two result locations.

Abstract: A circuit for a combined key value-dependent exchange and multiplicative randomization of two values comprises a first circuit for combined key value-dependent exchange and additive randomization configured to exchange the two values depending on a key value and randomize them by adding an additive randomization value to generate two additively randomized values and a second circuit configured to multiplicatively randomize the two additively randomized values by multiplying them with a multiplicative randomization value to generate two additively and multiplicatively randomized values and to remove the component of the additive randomization value multiplied by the multiplicative randomization value from the two additively and multiplicatively randomized values to generate two multiplicatively randomized values.

Abstract: A circuit includes a data input that is configured to receive a data word, the data word including at least one operand which is rotated by a number of bits given by a rotation parameter, a first control input that is configured to receive the rotation parameter, a second control input that is configured to receive an indication of an operation to be performed, a first subcircuit that is configured to generate an operation- and rotation-dependent bit mask from the rotation parameter and the indication of the operation to be performed, a second subcircuit which is configured to process the at least one operand as a function of the bit mask and the operation to be performed, wherein the operand and the operation result generated by the processing remain in the rotated state, and a data output which is configured to output the operation result.

Abstract: Processing of data stored in a memory, wherein the data are deleted depending on a functional setting if an operation is performed on the data.

Abstract: A cryptographic processing device for cryptographically processing data, having a memory configured to store a first operand and a second operand represented by the data to be cryptographically processed, wherein the first operand and the second operand each correspond to an indexed array of data words, and a cryptographic processor configured to determine, for cryptographically processing the data, a product of the first operand with the second operand by accumulating results of partial multiplications, each partial multiplication comprising the multiplication of a data word of the first operand with a data word of the second operand wherein the cryptographic processor is configured to perform the partial multiplications in successive blocks of partial multiplications, each block being associated with a result index range and a first operand index range and each block comprising all partial multiplications between data words of the first operand within the first operand index range with data words of the sec

Abstract: A circuit includes a data input that is configured to receive a data word, the data word including at least one operand which is rotated by a number of bits given by a rotation parameter, a first control input that is configured to receive the rotation parameter, a second control input that is configured to receive an indication of an operation to be performed, a first subcircuit that is configured to generate an operation- and rotation-dependent bit mask from the rotation parameter and the indication of the operation to be performed, a second subcircuit which is configured to process the at least one operand as a function of the bit mask and the operation to be performed, wherein the operand and the operation result generated by the processing remain in the rotated state, and a data output which is configured to output the operation result.

Abstract: According to an embodiment, a cryptographic processing device is described comprising a memory configured to store a first operand and a second operand and a cryptographic processor configured to determine, for cryptographically processing the data, the product of the first operand with the second operand by determining, for each result word index in a result word index range, a result data word for the result word index by accumulating products of sums of words of the first operand and the second operand and subtracting excess terms.

Abstract: A cryptographic processing device for cryptographically processing data, having a memory configured to store a first operand and a second operand represented by the data to be cryptographically processed, wherein the first operand and the second operand each correspond to an indexed array of data words, and a cryptographic processor configured to determine, for cryptographically processing the data, a product of the first operand with the second operand by accumulating results of partial multiplications, each partial multiplication comprising the multiplication of a data word of the first operand with a data word of the second operand wherein the cryptographic processor is configured to perform the partial multiplications in successive blocks of partial multiplications, each block being associated with a result index range and a first operand index range and each block comprising all partial multiplications between data words of the first operand within the first operand index range with data words of the sec