Patents by Inventor Erich William Gerbsch

Erich William Gerbsch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7095098
    Abstract: An electrically isolated and thermally conductive double-sided pre-packaged IC component, stamped lead members, drain pads, source pads, gate runner, and a MOSFET, IGBT, etc. are positioned between a pair of ceramic substrate members. Layers of solderable copper material are directly bonded to the inner and outer surfaces of the substrate members.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: August 22, 2006
    Assignee: Delphi Technologies, Inc.
    Inventors: Erich William Gerbsch, Ralph S. Taylor
  • Patent number: 6812553
    Abstract: An electrically isolated and thermally conductive double-sided pre-packaged IC component, stamped lead members, drain pads, source pads, gate runner, and a MOSFET, IGBT, etc. are positioned between a pair of ceramic substrate members. Layers of solderable cooper material are directly bonded to the inner and outer surfaces of the substrate members.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: November 2, 2004
    Assignee: Delphi Technologies, Inc.
    Inventors: Erich William Gerbsch, Ralph S. Taylor
  • Publication number: 20030132511
    Abstract: An electrically isolated and thermally conductive double-sided pre-packaged IC component, stamped lead members, drain pads, source pads, gate runner, and a MOSFET, IGBT, etc. are positioned between a pair of ceramic substrate members. Layers of solderable cooper material are directly bonded to the inner and outer surfaces of the substrate members.
    Type: Application
    Filed: January 16, 2002
    Publication date: July 17, 2003
    Inventors: Erich William Gerbsch, Ralph S. Taylor
  • Patent number: 6575765
    Abstract: An interconnect assembly and method for a semiconductor device, in which the interconnect assembly can be used in lieu of wirebond connections to form an electronic assembly. The interconnect assembly includes first and second interconnect members. The first interconnect member has a first surface with a first contact and a second surface with a second contact electrically connected to the first contact, while the second interconnect member has a flexible finger contacting the second contact of the first interconnect member. The first interconnect member is adapted to be aligned and registered with a semiconductor device having a contact on a first surface thereof, so that the first contact of the first interconnect member electrically contacts the contact of the semiconductor device.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: June 10, 2003
    Assignee: Delphi Technologies, Inc.
    Inventor: Erich William Gerbsch
  • Publication number: 20020106912
    Abstract: An interconnect assembly and method for a semiconductor device, in which the interconnect assembly can be used in lieu of wirebond connections to form an electronic assembly. The interconnect assembly includes first and second interconnect members. The first interconnect member has a first surface with a first contact and a second surface with a second contact electrically connected to the first contact, while the second interconnect member has a flexible finger contacting the second contact of the first interconnect member. The first interconnect member is adapted to be aligned and registered with a semiconductor device having a contact on a first surface thereof, so that the first contact of the first interconnect member electrically contacts the contact of the semiconductor device.
    Type: Application
    Filed: February 5, 2001
    Publication date: August 8, 2002
    Inventor: Erich William Gerbsch
  • Patent number: 6054765
    Abstract: A parallel dual switch module that is characterized by improved mechanical and electrical packaging efficiency and low cost. The module includes a common terminal defined by a first stamped elongate metal plate insert molded into the module housing, and positive and negative terminals defined by second and third stamped elongate metal plates disposed side-by-side atop the common terminal. Connection areas formed on the positive and negative terminals extend in opposite lateral directions, and interdigitate with connection areas formed on the common terminal, thereby forming two linear parallel rows of connection areas. Adjacent each row of connection areas, and mounted on a baseplate of the module is a set of parallel connected transistors subassemblies. A molded elongate gate collection component is mounted on the baseplate between the sets of transistor subassemblies, and beneath the common terminal.
    Type: Grant
    Filed: April 27, 1998
    Date of Patent: April 25, 2000
    Assignee: Delco Electronics Corporation
    Inventors: Charles Tyler Eytcheson, Monty Bradford Hayes, Lisa Ann Viduya, Roger Allen Mock, Eric Von Kierstead, Todd G. Nakanishi, Robert John Campbell, Erich William Gerbsch