Abstract: An improved method of stabilizing wet chemical baths is disclosed. Typically such baths are used in processes for treating workpieces, for example, plating processes for plating metal onto substrates. In particular, the present invention relates to copper plating baths. More particularly, the present invention relates to the stability of copper plating baths. More particularly, the present invention relates to prevention of void formation by monitoring the accumulation of deleterious by-products in copper plating baths.

Abstract: Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.

Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 ?m and via openings filled with electroplated copper than is substantially free of internal seams or voids.

Abstract: A method for manufacturing high performance copper inductors includes providing a tall, Cu laminate spiral inductor is formed at the last metal level, and at the last metal +1 level, with the metal levels being interconnected by a bar via having the same spiral shape as the spiral metal inductors at the last metal level and the last metal +1 level. The method includes integrating the formation of thick inductors with the formation of bond pads, terminals and interconnect wiring with the last metal +1 wiring. Included are dielectric deposition and spacer formation steps, and/or selective deposition of a passivating metal such as CoWP, to passivate a Cu inductor that is formed after the last metal layer.

Abstract: A method for manufacturing a self-compensating resistor within an integrated circuit is disclosed. The self-compensating resistor includes a first resistor and a second resistor. The first resistor having a first resistance value is initially formed, and then the second resistor having a second resistance value is subsequently formed. The second resistor is connected in series with the first resistor. The second resistance value is less than the first resistance value, but the total resistance value of the first and second resistors lies beyond a desired target resistance range. Finally, an electric current is sent to the second resistor to change the dimension of the second resistor such that the total resistance value of the first and second resistors falls within the desired target resistance range.

Abstract: An intermediate semiconductor structure and method for low-pressure wire bonding that reduces the propensity of dielectric material to mechanical failure due to any wire bonding stresses. Roughened surfaces such as metal pillars or metal dendrites are provided on a bonding pad, bonding wire or both. These roughened surfaces increase reactivity between the bond wire and the bond pad to form strong bonds. This increased activity as a result of the roughened bonding pad and/or wire surfaces reduce the amount of pressure, temperature and energy required for wire bonding, which in turn, avoids damage to the bonding pad as well as the semiconductor substrate.

Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 &mgr;m and via openings filled with electroplated copper than is substantially free of internal seams or voids.

Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 &mgr;m and via openings filled with electroplated copper than is substantially free of internal seams or voids.

Abstract: The present invention provides a method of selectively inhibiting the deposition of a conductive material within desired regions of a semiconductor device. A seed layer is rendered ineffective to the electroplating in select regions of the substrate, by either the removal or the poisoning of the seed layer in select regions.

Abstract: A method for controlling the composition of a chemical bath in which predictive dosing is used to account for changes in the composition of the bath in which the operating characteristics of the process are partitioned into a plurality of operating modes and the consumption or generation of materials related to the process are determined empirically and additions of material are made as appropriate.

Abstract: A method and apparatus are provided for the electroplating of a substrate such as a semiconductor wafer which provides a uniform electroplated surface and minimizes bum-through of a seed layer used on the substrate to initiate electroplating. The method and apparatus of the invention uses a specially defined multistep electroplating process wherein, in one aspect, a voltage below a predetermined threshold voltage is applied to the anode and cathode for a first time period followed by applying a current to the anode and cathode for a second time period the current producing a voltage below the predetermined threshold voltage. In another aspect of the invention, a current is applied to the anode and cathode substrate which current is preprogrammed to ramp up to a current value from a first current value which current produces a voltage below a predetermined threshold voltage.

Abstract: A method and apparatus for Chemical-Mechanical Polishing of semiconductor wafers using various formulations of high viscosity slurry.

Abstract: A shortened fuse link is disclosed. The fuse link comprises a first and second interconnect, with interconnects each being substantially longer than deep. The interconnects are disposed toward each other with a insulator region between them. A fusible conductor, spanning the insulator region, is attached at the top of the interconnects. The present device allows the length of the fusible conductor to be shortened, and results in a fuse link that can be consistently blown with a single laser pulse. Additionally, the fuse link can be used in a staggered layout. The staggered layout of parallel fuse links allows a high number of links in a relatively small area, with or without the use of tungsten barriers, and allows accessing all fuse links through a single fuse blow window.

Abstract: An apparatus for polishing a semiconductor wafer is provided comprising a wafer carrier to provide a force against a wafer and a rotating polishing pad during the polishing operation and a polishing slurry distributor device disposed to provide a spray of the slurry on the polishing pad. The wafer is polished using less slurry than a conventional polishing apparatus while still maintaining the polishing rates and polishing uniformity of the prior art polishing apparatus. A preferred spraying means is a closed elongated tube having a plurality of openings which tube is positioned over at least one-half the diameter of the polishing pad and a polishing slurry under pressure is directed onto the surface of the pad, preferably in a substantially transverse spray stream.

Abstract: A desired reagent is delivered to a workpiece undergoing a chemical mechanical polishing process with a chemical mechanical planarization apparatus. A slurry and polishing pad are provided for the polishing process. Reagent containing microcapsules are also provided, the microcapsules encapsulating a desired reagent. The workpiece is polished with a combination of the slurry, the polishing pad, and the microcapsules, wherein the encapsulated reagents are controllably released during the polishing step via manipulation of a polishing parameter. In one embodiment, the microcapsules are included in the slurry. In an alternate embodiment, the microcapsules are embedded within the polishing pad.

Abstract: A gas discharge illumination device is prepared by encapsulating ionizable gas within microporous or nanoscale sealed cavities created within a matrix material. Upon exposure of said matrix material to an electric field, the ionizable gas becomes ionized and emits light. By incorporating several different ionizable gases into one matrix material, a display with different colors of light can be produced. The gas discharge illumination device can be fabricated by a variety of techniques including selective cavity formation with overcoating taking place in an ionizable gas ambient, and bubbling ionizable gas through the matrix material while it is in viscous form. The gas discharge illumination device can be used to form either active or passive displays, as a sensor for detecting electric fields, and in other applications.

Abstract: A process for stripping thin layers of oxide such as sacrificial pad oxide employs etching chemistry that widens cracks to remove shallow cracks and limit the widening of deep cracks, thereby producing a final oxide surface on thick layers of oxide that is less rough than prior art methods and enabling the fabrication of oxide-filled trenches that have geometries and/or surface smoothness that were previously impossible.

Abstract: The fuse link includes a first and second interconnect, with interconnects each being substantially longer than deep. The interconnects are disposed toward each other with a insulator region between them. A fusible conductor, spanning the insulator region, is attached at the top of the interconnects. The present device allows the length of the fusible conductor to be shortened, and results in a fuse link that can be consistently blown with a single laser pulse. Additionally, the fuse link can be used in a staggered layout. The staggered layout of parallel fuse links allows a high number of links in a relatively small area, with or without the use of tungsten barriers, and allows accessing all fuse links through a single fuse blow window.

Abstract: The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures.Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.

Abstract: The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures.Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.