Abstract: A network device can place some or all of the packet processing pipeline into a low-power state for detected idle intervals of sufficient duration. The network device detects idleness greater than a critical duration and automatically engages a low-power mode involving clock throttling and/or clock gating. The power savings in the packet processing pipeline in the network device is based on the average long-term residency in idleness. The idle power is reduced for the packet processing pipeline in the network device by detecting average long-term idleness as a function of the minimum latency of the packet processing pipeline, which is used to reduce the clock rate of the packet processing pipeline, thereby resulting in power savings for the network device.

Abstract: An error handling device logs errors in a computing system including a plurality of devices connected to the error handling device. The error handling device provides groups of error registers. Each group of error registers is associated with a value of a plurality of values. Each of the devices that communicate errors to the error handling device are associated with one of the values. The error handling device receives error messages from the devices connected to the error handling device and for each received error message of the received error messages, determines a value of the plurality of values associated with the device transmitting the received error message, determines the group of error registers associated with the determined value, and log the received error message in the determined group of error registers.

Abstract: Technologies for processing network packets by a network interface controller (NIC) of a computing device include a network interface, a packet processor, and a controller device of the NIC, each communicatively coupled to a memory fabric of the NIC. The packet processor is configured to receive an event message from the memory fabric and transmit a message to the controller device, wherein the message indicates the network packet has been received and includes the memory fabric location pointer. The controller device is configured to fetch at least a portion of the received network packet from the memory fabric, write an inbound descriptor usable by one or more on-die cores of the NIC to perform an operation on the fetched portion, and restructure the network packet as a function of an outbound descriptor written by the on-die cores subsequent to performing the operation. Other embodiments are described herein.

Abstract: An error handling device logs errors in a computing system including a plurality of devices connected to the error handling device. The error handling device provides groups of error registers. Each group of error registers is associated with a value of a plurality of values. Each of the devices that communicate errors to the error handling device are associated with one of the values. The error handling device receives error messages from the devices connected to the error handling device and for each received error message of the received error messages, determines a value of the plurality of values associated with the device transmitting the received error message, determines the group of error registers associated with the determined value, and log the received error message in the determined group of error registers.

Abstract: Technologies for processing network packets by a network interface controller (NIC) of a computing device include a network interface, a packet processor, and a controller device of the NIC, each communicatively coupled to a memory fabric of the NIC. The packet processor is configured to receive an event message from the memory fabric and transmit a message to the controller device, wherein the message indicates the network packet has been received and includes the memory fabric location pointer. The controller device is configured to fetch at least a portion of the received network packet from the memory fabric, write an inbound descriptor usable by one or more on-die cores of the NIC to perform an operation on the fetched portion, and restructure the network packet as a function of an outbound descriptor written by the on-die cores subsequent to performing the operation. Other embodiments are described herein.

Abstract: In some embodiments, a multi-phase converter with dynamic phase adjustment is provided. In some embodiments, a controller may include circuitry to control how many phase legs are active based on output current and also which phase legs are to be enabled.

Abstract: Inductors packaged with a voltage regulator for an integrated circuit within the same package are deposited to a sufficient thickness to reduce resistance and improve the quality factor. Furthermore, the voltage regulator switches currents through the inductors at a relatively high frequency such that the overall size and inductances of the inductors may be reduced. As a consequence, integrating both the integrated circuits including a voltage regulator and associated inductor array in a single package is facilitated. Other embodiments are described and claimed.

Abstract: A configurable power control system is disclosed. The power control system can include a control module, an enable/disable module coupled to a power rail (i.e. an internal power line) to enable and disable power to the power rail. The system can also include a sequencer module coupled to the first and a second power rail to sequence power to the power rail(s). The system can also include a fault detect module to detect system parameters. Additionally, the system can include a memory module to store user input and can store detected faults to be utilized by the control module and other modules to control interrelationships between the enable module, the sequencer module, the fault detect module, power in, and power provided via the power rails.

Abstract: Inductors packaged with a voltage regulator for an integrated circuit within the same package are deposited to a sufficient thickness to reduce resistance and improve the quality factor. Furthermore, the voltage regulator switches currents through the inductors at a relatively high frequency such that the overall size and inductances of the inductors may be reduced. As a consequence, integrating both the integrated circuits including a voltage regulator and associated inductor array in a single package is facilitated. Other embodiments are described and claimed.

Abstract: In some embodiments, a multi-phase converter with dynamic phase adjustment is provided.

Abstract: A configurable power control system is disclosed. The power control system can include a control module, an enable/disable module coupled to a power rail (i.e. an internal power line) to enable and disable power to the power rail. The system can also include a sequencer module coupled to the first and a second power rail to sequence power to the power rail(s). The system can also include a fault detect module to detect system parameters. Additionally, the system can include a memory module to store user input and can store detected faults to be utilized by the control module and other modules to control interrelationships between the enable module, the sequencer module, the fault detect module, power in, and power provided via the power rails.

Abstract: Disclosed is a digitally controlled multi-phase voltage regulator system providing regulated power to electronic components that have variable power requirements. Power is supplied by one or more power integrated circuits (IC) each having a high side power switch controlled by pulse width modulated signals and a low side power switch. The power IC senses voltage at the load and has an on-chip current mirror for generating a current that is a ratio of current delivered to the load. The power IC also has current limiting and on-chip temperature sensing components. The voltage and current information is digitized and provided to a control integrated circuit (IC). The control IC receives this digitized information as well as user provided parameters and, in the regulation mode of operation, provides digitized pulse width modulated control signals to the power IC. In an active transient response mode of operation, the control IC provides signals to turn either the high side switches or low side switches ON.

Abstract: A system and method for detecting, measuring, and reporting a time derivate of a current signal (di/dt). A sensing element detects current from a load. The sensing element includes an inductor. The inductor is located in series with the load and includes associated parasitic resistance. A differential potential develops across the inductor and the parasitic resistance. The differential potential is amplified and converted to a single-ended value. The single-ended value is then fed to an analog to digital converter that provides an output representative of di/dt.

Abstract: Disclosed is a digitally controlled multi-phase voltage regulator system providing regulated power to electronic components that have variable power requirements. Power is supplied by one or more power integrated circuits (IC) each having a high side power switch controlled by pulse width modulated signals and a low side power switch. The power IC senses voltage at the load and has an on-chip current mirror for generating a current that is a ratio of current delivered to the load. The power IC also has current limiting and on-chip temperature sensing components. The voltage and current information is digitized and provided to a control integrated circuit (IC). The control IC receives this digitized information as well as user provided parameters and, in the regulation mode of operation, provides digitized pulse width modulated control signals to the power IC. In an active transient response mode of operation, the control IC provides signals to turn either the high side switches or low side switches ON.

Abstract: A logic state transition sensor circuit. The logic state transition sensor circuit detects and records transitions in voltage corresponding to a transition of a digital logic state (high to low; low to high). The logic state transition sensor circuit may include a sensing circuit containing sensing and amplification elements and a recording circuit containing recording elements. When a logic state transition occurs at an input of the sensing circuit, a positive logic pulse may be generated. Propagation of the logic pulse to the recording circuit causes a charge to be transferred to an output stage capacitor. Repeated logic state transitions cause similar incremental increases in the charge of the output stage capacitor. Charge transfer is governed by ratios of capacitors internal to the recording circuit and hence may be insensitive to process variation. The output stage capacitor may output a voltage representative of a number of logic state transitions sensed.

Abstract: A data comparator that operates on an input voltage signal and a reference voltage signal is disclosed. Internally, the comparator includes replicated circuitry to produce differential gain. Each set of replicated circuitry includes two gain stages for high amplification, high sampling rate, and for reducing kickback noise at the input voltage signal and the reference voltage signal. The comparator may further include self-biased CMOS inverters for cancellation of input offset error and a rail-to-rail regenerative output latch. The circuit can also include a comparator bias circuit that can improve the speed of the auto-zero operation.

Abstract: A data comparator that operates on an input voltage signal and a reference voltage signal is disclosed. Internally, the comparator includes replicated circuitry to produce differential gain. Each set of replicated circuitry includes two gain stages for high amplification, high sampling rate, and for reducing kickback noise at the input voltage signal and the reference voltage signal. The comparator may further include self-biased CMOS inverters for cancellation of input offset error and a rail-to-rail regenerative output latch. The circuit can also include a comparator bias circuit that can improve the speed of the auto-zero operation.

Abstract: A logic state transition sensor circuit. The logic state transition sensor circuit detects and records transitions in voltage corresponding to a transition of a digital logic state (high to low; low to high). The logic state transition sensor circuit may include a sensing circuit containing sensing and amplification elements and a recording circuit containing recording elements. When a logic state transition occurs at an input of the sensing circuit, a positive logic pulse may be generated. Propagation of the logic pulse to the recording circuit causes a charge to be transferred to an output stage capacitor. Repeated logic state transitions cause similar incremental increases in the charge of the output stage capacitor. Charge transfer is governed by ratios of capacitors internal to the recording circuit and hence may be insensitive to process variation. The output stage capacitor may output a voltage representative of a number of logic state transitions sensed.

Abstract: A system and method for detecting, measuring, and reporting a time derivate of a current signal (di/dt) is provided. A sensing element detects current from a load. The sensing element includes an inductor. The inductor is located in series with the load and includes associated parasitic resistance. A differential potential develops across the inductor and the parasitic resistance. The differential potential is amplified and converted to a single-ended value. The single-ended value is then fed to an analog to digital converter that provides an output representative of di/dt.

Abstract: A power distribution management apparatus for supplying power to two or more loads includes a power and clock distribution controller capable of determining voltage, current and clock signal frequency targets for the loads. The apparatus also includes two or more power sources responsive to the controller so as to be selectively coupled with the loads to provide the target voltage and current to the loads. The power sources have switching frequencies of at least one megahertz. The apparatus further includes two or more clock signal sources responsive to the controller and coupled with the loads so as to provide clock signals to the loads at the target frequencies.