Patents by Inventor Erik Altman
Erik Altman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7496733Abstract: A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which renames registers and determines if dependencies exist. A functional unit provides pointer information updates to the pointer register stage such that pointer information is processed and updated to the pointer register stage before or in parallel with the register dependency checking.Type: GrantFiled: October 26, 2007Date of Patent: February 24, 2009Assignee: International Business Machines CorporationInventors: Erik Altman, Michael Karl Gschwind, Jude A. Rivers, Sumedh Wasudeo Sathaye, John-David Wellman, Victor Zyuban
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Publication number: 20080065861Abstract: This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.Type: ApplicationFiled: October 31, 2007Publication date: March 13, 2008Inventors: Erik Altman, Michael Gschwind, David Luick, Daniel Prener, Jude Rivers, Sumedh Sathaye, John-David Wellman
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Publication number: 20080052495Abstract: A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which renames registers and determines if dependencies exist. A functional unit provides pointer information updates to the pointer register stage such that pointer information is processed and updated to the pointer register stage before or in parallel with the register dependency checking.Type: ApplicationFiled: October 26, 2007Publication date: February 28, 2008Inventors: ERIK ALTMAN, Michael Gschwind, Jude Rivers, Sumedh Sathaye, John-David Wellman, Victor Zyuban
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Patent number: 7325124Abstract: A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which renames registers and determines if dependencies exist. A functional unit provides pointer information updates to the pointer register stage such that pointer information is processed and updated to the pointer register stage before or in parallel with the register dependency checking.Type: GrantFiled: April 21, 2004Date of Patent: January 29, 2008Assignee: International Business Machines CorporationInventors: Erik Altman, Michael Karl Gschwind, Jude A. Rivers, Sumedh Wasudeo Sathaye, John-David Wellman, Victor Zyuban
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Publication number: 20070162895Abstract: A trace cache system is provided comprising a trace start address cache for storing trace start addresses with successor trace start addresses, a trace cache for storing traces of instructions executed, a trace history table (THT) for storing trace numbers in rows, a branch history shift register (BHSR) or a trace history shift register (THSR) that stores histories of branches or traces executed, respectively, a THT row selector for selecting a trace number row from the THT, the selection derived from a combination of a trace start address and history information from the BHSR or the THSR, and a trace number selector for selecting a trace number from the selected trace number row and for outputting the selected trace number as a predicted trace number.Type: ApplicationFiled: January 10, 2006Publication date: July 12, 2007Applicant: International Business Machines CorporationInventors: Erik Altman, Michael Gschwind, Jude Rivers, Sumedh Sathaye, John-David Wellman, Victor Zyuban
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Publication number: 20070130237Abstract: A method and apparatus for storing non-critical processor information without imposing significant costs on a processor design is disclosed. Transient data are stored in the processor-local cache hierarchy. An additional control bit forms part of cache addresses, where addresses having the control bit set are designated as “transient storage addresses.” Transient storage addresses are not written back to external main memory and, when evicted from the last level of cache, are discarded. Preferably, transient storage addresses are “privileged” in that they are either not accessible to software or only accessible to supervisory or administrator-level software having appropriate permissions. A number of management functions/instructions are provided to allow administrator/supervisor software to manage and/or modify the behavior of transient cache storage.Type: ApplicationFiled: December 6, 2005Publication date: June 7, 2007Inventors: Erik Altman, Michael Gschwind, Robert Montoye, Jude Rivers, Sumedh Sathaye, John-David Wellman, Victor Zyuban
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Publication number: 20060190614Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.Type: ApplicationFiled: February 24, 2005Publication date: August 24, 2006Inventors: Erik Altman, Peter Capek, Michael Gschwind, Charles Johns, Harm Hofstee, Martin Hopkins, James Kahle, Sumedh Sathaye, John-David Wellman
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Publication number: 20060190700Abstract: A method for handling permanent and transient errors in a microprocessor is disclosed. The method includes reading a scalar value and a scalar operation from an execution unit of the microprocessor. The method further includes writing a copy of the scalar value into each of a plurality of elements of a vector register of a Single Instruction Multiple Data (SIMD) unit of the microprocessor and executing the scalar operation on each scalar value in each of the plurality of elements of the vector register of the SIMED unit using a vector operation. The method further includes comparing each result of the scalar operation on each scalar value in each of the plurality of elements of the vector register and detecting a permanent or transient error if all of the results are not identical.Type: ApplicationFiled: February 22, 2005Publication date: August 24, 2006Inventors: Erik Altman, Gheorghe Cascaval, Luis Ceze, Vijayalakshmi Srinivasan
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Publication number: 20060174089Abstract: A method, system, and computer program product for mixing of conventional and augmented instructions within an instruction stream, wherein control may be directly transferred, without operating system intervention, between one type of instruction to another. Extra instruction word bits are added in a manner that is designed to minimally interfere with the encoding, decoding, and instruction processing environment in a manner compatible with existing conventional fixed instruction width code. A plurality of instruction words are inserted into an instruction word oriented architecture to form an encoding group of instruction words. The instruction words in the encoding group are dispatched and executed either independently or in parallel based on a specific microprocessor implementation. The encoding group does not indicate any form of required parallelism or sequentiality. One or more indicators for the encoding group are created, wherein one indicator is used to indicate presence of the encoding group.Type: ApplicationFiled: February 1, 2005Publication date: August 3, 2006Applicant: International Business Machines CorporationInventors: Erik Altman, Michael Gschwind, Daniel Prener, Jude Rivers, Sumedh Sathaye, John-David Wellman, Victor Zyuban
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Publication number: 20060155965Abstract: A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.Type: ApplicationFiled: January 12, 2005Publication date: July 13, 2006Applicant: International Business Machines CorporationInventors: Erik Altman, Michael Gschwind, Jude Rivers, Sumedh Sathaye, John-David Wellman, Victor Zyuban
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Publication number: 20050251654Abstract: A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which renames registers and determines if dependencies exist. A functional unit provides pointer information updates to the pointer register stage such that pointer information is processed and updated to the pointer register stage before or in parallel with the register dependency checking.Type: ApplicationFiled: April 21, 2004Publication date: November 10, 2005Inventors: Erik Altman, Michael Gschwind, Jude Rivers, Sumedh Sathaye, John-David Wellman, Victor Zyuban
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Publication number: 20050132172Abstract: A method and apparatus is provided to manage data in computer registers in a program, making more computer registers available to one or more programmers utilizing a name level instruction. The method and apparatus disclosed herein presents a way of reducing the overhead of register management, by introducing a concept of a name level for each of the named architected registers in a processor. The method provides a programmer with a larger register name-space while not increasing the size of the instruction word in the processor instruction-set architecture. It also provides for the facilitation of architectural features which overload the architected register namespace and ease the overhead of register management. This provides for the addition of more computer registers without changing the instruction format of the computer.Type: ApplicationFiled: December 12, 2003Publication date: June 16, 2005Inventors: Alexandre Eichenberger, Erik Altman, Sumedh Sathaye, John-David Wellman
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Publication number: 20050114629Abstract: This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.Type: ApplicationFiled: November 24, 2003Publication date: May 26, 2005Inventors: Erik Altman, Michael Gschwind, David Luick, Daniel Prener, Jude Rivers, Sumedh Sathaye, John-David Wellman
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Patent number: 6381691Abstract: A method is provided for scheduling instructions for execution along multiple paths in a Computer processing system implementing out-of-order execution. The method includes the step of selecting and moving a next instruction from its current position in a sequence of instructions to an earlier position. It is determined whether the selected instruction may reference a memory location for read-access. It is determined whether the selected instruction was previously moved over a non-selected instruction which may ambiguously reference the memory location, when the selected instruction may reference the memory location for read-access. It is determined whether the selected instruction was previously moved over a branch instruction, when the selected instruction was previously moved over the non-selected instruction. A record of the selected instruction is stored for future reference, when the selected instruction was previously moved over the branch instruction.Type: GrantFiled: August 13, 1999Date of Patent: April 30, 2002Assignee: International Business Machines CorporationInventors: Erik Altman, Michael K. Gschwind
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Patent number: 6349361Abstract: There is provided a method for reordering and renaming memory references in a multiprocessor computer system having at least a first and a second processor. The first processor has a first private cache and a first buffer, and the second processor has a second private cache and a second buffer. The method includes the steps of, for each of a plurality of gated store requests received by the first processor to store a datum, exclusively acquiring a cache line that contains the datum by the first private cache, and storing the datum in the first buffer. Upon the first buffer receiving a load request from the first processor to load a particular datum, the particular datum is provided to the first processor from among the data stored in the first buffer based on an in-order sequence of load and store operations.Type: GrantFiled: March 31, 2000Date of Patent: February 19, 2002Assignee: International Business Machines CorporationInventors: Erik Altman, Kemal Ebcioglu, Michael Gschwind, Sumedh Sathaye