Abstract: Technologies for hybrid sleep power management include a computing device with a processor supporting a low-power idle state. In a pre-boot firmware environment, the computing device reserves a memory block for firmware use and copies platform wake code to a secure memory location, such as system management RAM (SMRAM). At runtime, an operating system may execute with the processor in protected mode. In response to a request to enter a sleep or suspend state, the computing device generates a system management interrupt (SMI). In an SMI handler, the computing device copies the wake code from SMRAM to the reserved memory block. The computing device resumes from the SMI handler to the wake code with the processor in real mode. The wake code enters the low-power idle state and then jumps to a wake vector of the operating system after receiving a wake event. Other embodiments are described and claimed.

Abstract: Technologies for hybrid sleep power management include a computing device with a processor supporting a low-power idle state. In a pre-boot firmware environment, the computing device reserves a memory block for firmware use and copies platform wake code to a secure memory location, such as system management RAM (SMRAM). At runtime, an operating system may execute with the processor in protected mode. In response to a request to enter a sleep or suspend state, the computing device generates a system management interrupt (SMI). In an SMI handler, the computing device copies the wake code from SMRAM to the reserved memory block. The computing device resumes from the SMI handler to the wake code with the processor in real mode. The wake code enters the low-power idle state and then jumps to a wake vector of the operating system after receiving a wake event. Other embodiments are described and claimed.

Abstract: A mechanism is described for facilitating faster suspend/resume operations in computing systems according to one embodiment of the invention. A method of embodiments of the invention includes initiating an entrance process into a first sleep state in response to a sleep call at a computing system, transforming from the first sleep state to a second sleep state. The transforming may include preserving at least a portion of processor context at a local memory associated with one or more processor cores of a processor at the computing system. The method may further include entering the second sleep state.

Abstract: A mechanism is described for facilitating faster suspend/resume operations in computing systems according to one embodiment of the invention. A method of embodiments of the invention includes initiating an entrance process into a first sleep state in response to a sleep call at a computing system, transforming from the first sleep state to a second sleep state. The transforming may include preserving at least a portion of processor context at a local memory associated with one or more processor cores of a processor at the computing system. The method may further include entering the second sleep state.