Abstract: A filter configuration for a demodulated QAM signal has a first channel for a cosine demodulated component of the QAM signal, a second channel for a sine demodulated component of the QAM signal, a filter circuit, which receives the two signal components and for each signal component has one transfer function that is composed of terms in phase with this signal component and terms phase-shifted from it by &pgr;/2 and/or −&pgr;/2. The circuit configuration also includes a cross branch for picking up signal portions from the respectively other channel that correspond to the phase-shifted terms of the transfer function. In a first state, the circuit configuration connects the input of the cross branch to the first channel and the output of the cross branch to the second channel, and in a second state connects the input of the cross branch to the second channel and the output of the cross branch to the first channel. A slope detector especially suitable for use with this filter configuration is also provided.

Abstract: An apparatus has a clock monitoring device, which determines whether or not the clock rate of an input clock signal (.PHI..sub.0) has fallen below a predetermined minimum clock rate. A system is provided which, from the input clock signal, forms a master clock signal (.PHI..sub.m) and a slave clock signal (.PHI..sub.s) which are in a form such that both the switches (S1) of dynamic master registers (ML) and the switches (S2) of dynamic slave registers (SL) are closed provided that the clock rate has fallen below the minimum clock rate. Otherwise, at most either the switches (S1) of the dynamic master latches (ML) or the switches (S2) of the dynamic slave latches (SL) are closed. The primary advantage achieved hereby is that in the event of failure of the input clock signal, in particular in circuits with a high degree of pipelining, undefined register states do not result in an impermissibly high current consumption.

Abstract: The integrated circuit with a clock system, particularly a CMOS circuit with extensive pipelining, whereby an optimally low overall dissipated power is effected in that a clock driver circuit is provided with a specifically wired driver output stage that generates a clock supply voltage that corresponds to about half the value of a general supply voltage. A great reduction of the dissipated power can be achieved given relative slight sacrifices in the performance capability.

Abstract: A series of adders (AD.sub.i) with inputs for binary number bits of the same significance, which output intermediate sum and carry words that are combined to form sum words, are provided for the bit-parallel addition of binary numbers in two's complement with carry-save overflow correction. For the correction of overflow errors, the carry bit of the adder (AD.sub.n-2) having the second highest significance is replaced by the carry bit of the most significant adder (AD.sub.n-1) and, in case the carry bits of the two most significant adders (AD.sub.n-1, AD.sub.n-2) are unequal, the intermediate sum bit of the most significant adder (AD.sub.n-1) is replaced by the carry bit thereof. The element AD.sub.kn-1 has the same number of transistors as the other adders AD.sub.0 . . . AD.sub.n-2.

Abstract: ECL-compatible input/output circuits in CMOS technology which meet very strict ECL level demands and are as independent as possible of temperature and field effect transistor parameter fluctuations. This is achieved by a control circuit for reference currents of the current mirror circuits. The control circuit is composed of a sensor stage, of a comparator, of a low-pass filter and of a reference current source. Current mirror circuits are also utilized in the driver stages and in the sensor stage.