Abstract: A multiprocessing computer system employing a three-hop communications protocol. When a request is sent by a requesting node to a home node, the home node sends read and/or invalidate demands to any slave nodes holding cached copies of the requested data. The demands from the home node to the slave nodes may each advantageously include a value indicative of the number of replies the requesting agent should expect to receive. The slaves reply back to the requesting node with either data or an acknowledge. Each reply may further include the number of replies the requester should expect. Upon receiving all expected replies, the requesting node may send a completion message back to the home and may treat the transaction as completed and proceed with subsequent processing.

Abstract: An apparatus and method for facilitating the sharing of memory blocks between a computer node and an external device irrespective whether the external device and the common bus both employ a common protocol and irrespective whether the external device and the common bus both operate at the same speed. Each of the memory blocks has a local physical address at a memory module of the computer node and an associated memory tag (Mtag) for tracking a state associated with that memory block, including a state for indicating whether that memory block is exclusive to the computer node, a state for indicating whether that memory block is shared by the computer node with the external device, and a state for indicating whether that memory block is invalid in the computer node. The apparatus includes receiver logic configured to receive, when coupled to the common bus of the computers node, memory access requests specific to the apparatus on the common bus.

Abstract: A computer system includes multiple local buses to which processors and other devices may be connected. A repeater is coupled to each of the local buses. Additionally, a top level repeater is coupled to each of the repeaters. The repeaters transmit transactions from the corresponding local buses to the top repeater. The top repeater, based upon the local or global nature of the transaction, transmits the transaction to one or more of the repeaters. The repeaters receiving the transaction then transmit the transaction upon the local buses attached thereto. If the transaction is a local transaction, the top repeater transmits the transaction to those repeaters which are configured into a local domain with the repeater which detected the initial transaction. The local domain comprises one or more repeaters which are logically interconnected. The local buses attached thereto logically form one SMP bus to which devices may be attached. Alternatively, the transaction may be a global transaction.

Abstract: A flexible scheme is provided for designating the appropriate write-back protocol best suited for each memory level within a multi-level-cache computer system. The skip-level memory hierarchy of the present invention includes a lower-level copy-back cache and a higher-level write-through cache. This greatly simplifies the implementation of the higher-level cache, since it may be implemented with a write-or-read access to its address tag. Although counterintuitive, a write-through higher-level cache in a distributed shared memory may also increase the efficiency of the computer system without unduly increasing the volume of network traffic within the computer system. This is because a write-through higher-level cache increases the probability of readily-available cached copies of updated data which are consistent with the home copies of the data, thereby reducing the number of fetches from remote home locations whenever the data is not found in the lower-level cache but is found in the higher-level cache.

Abstract: A multiprocessing computer system employing a three-hop communications protocol including a reply count communication. When a request is sent by a requesting node to a home node, the home node sends read and/or invalidate demands to any slave nodes holding cached copies of the requested data. The demands from the home node the slave nodes may each advantageously include a value indicative of the number of replies the requesting agent should expect to receive. The slaves reply back to the requesting node with either data or an acknowledge. Each reply may further include the number of replies the requester should expect. Upon receiving all expected replies, the requesting node may send a completion message back to the home and may treat the transaction as completed and proceed with subsequent processing.

Abstract: A computer system optimized for block copy operations is provided. In order to perform a block copy from a remote source block to a local destination block, a processor within a local node of the computer system performs a specially coded write operation. The local node, upon detection of the specially coded write operation, performs a read operation to the source block in the remote node. Concurrently, the write operation is allowed to complete in the local node such that the processor may proceed with subsequent computing tasks while the local node completes the copy operation. The read from the remote node and subsequent storage of the data in the local node is completed by the local node, not by the processor. In one specific embodiment, the specially coded write operation is indicated using certain most significant bits of the address of the write operation.

Abstract: An efficient cache allocation scheme is provided for both uniprocessor and multiprocessor computer systems having at least one cache. In one embodiment, upon the detection of a cache miss, a determination of whether the cache miss is "avoidable" is made. In other words, would the present cache miss have occurred if the data had been cached previously and if the data had remained in the cache. One example of an avoidable cache miss in a multiprocessor system having a distributed memory architecture is an excess cache miss. An excess cache miss is either a capacity miss or a conflict miss. A capacity miss is caused by the insufficient size of the cache. A conflict miss is caused by insufficient depth in the associativity of the cache. The determination of the excess cache miss involves tracking read and write requests for data by the various processors and storing some record of the read/write request history in a table or linked list. Data is cached only after an avoidable cache miss has occurred.

Abstract: An efficient streamlined cache coherent protocol for replacing data is provided in a multiprocessor distributed-memory computer system. In one implementation, the computer system includes a plurality of subsystems, each subsystem includes at least one processor and an associated cache and directory. The subsystems are coupled to a global interconnect via global interfaces. In one embodiment, when data is replaced from a requesting subsystem, an asynchronous flush operation is initiated. In this implementation, the flush operation includes a pair of decoupled local flush instruction and corresponding global flush instruction. By decoupling the local flush instructions from the global flush instructions, once the requesting processor in the requesting subsystem is done issuing the local flush instruction, the requesting processor does not have to wait for a corresponding response from home location associated with the data being replaced.

Abstract: A multiprocessing computer system employs local and global address spaces and Non- Uniform Memory Architecture (NUMA) and Cache-Only Memory Architecture (COMA) access modes. The multiprocessing computer architecture employs a plurality of processing nodes. When a processing node initiates a memory transaction, the node determines whether the address of the memory transaction is a global address or a local physical address. If the address is a global address, a NUMA coherency request is initiated. Alternatively, if the address is a local physical address, a COMA coherency request is initiated. The nodes additionally include local physical address to global address translation units. The local physical address to global address translation units are configured to translate a local physical address to a corresponding global address prior to initiating a COMA coherency request.

Abstract: A computer system includes multiple processing nodes, each of which is divided into subnodes. Transactions from a particular subnode are performed in the order presented by that subnode. Therefore, when a first transaction from the subnode is delayed to allow performance of coherency activity with other processing nodes, subsequent transactions from that subnode are delayed as well. Additionally, coherency activity for the subsequent transactions may be initiated in accordance with a prefetch method assigned to the subsequent transactions. In this manner, the delay associated with the ordering constraints of the system may be concurrently experienced with the delay associated with any coherency activity which may need to be performed in response to the subsequent transactions. In order to respect the ordering constraints imposed by the computer system, a system interface within the processing nodes employs an early completion policy for prefetch operations.

Abstract: A computer system including one or more processing nodes, each of which includes one or more subnodes is provided. One of the subnodes (the controller subnode) manages the interface between the processing node and the remainder of the computer system. Other subnodes (snooper subnodes) are employed to store access rights for coherency units within the memory. The processing node's memory is logically divided into portions, and each subnode stores access rights for a particular memory portion. When a transaction is initiated within the processing node, the subnode storing the access rights for the coherency unit affected by the transaction analyzes the access rights and determines if the transaction may complete locally within the processing node. If coherency activity is required, the subnode asserts an ignore signal causing the transaction to be omitted while coherency activity is performed to acquire sufficient access rights.

Abstract: A method in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes for servicing a first memory access request by a first node of the computer network pertaining to a memory block having a home node different from the first node in the computer network. The computer network has no natural ordering mechanism and natural broadcast for servicing memory access requests from the plurality of nodes. The home node has no centralized directory for tracking states of the memory block in the plurality of nodes. The method includes the step of receiving via the common network infrastructure at the home node from the first node the first memory access request for the memory block.

Abstract: A method, in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the first plurality of nodes, for servicing a memory access request by a first node of the first plurality of nodes. The memory access request pertains to a memory block of a memory module that has a home node different from the first node in the computer network. The home node has a partial directory cache that has fewer directory cache entries than a total number of memory blocks in the memory module. The method includes the step of ascertaining whether the memory block is currently cached in the partial directory cache. If the memory block is currently cached in the partial directory cache, the first memory access request is serviced using a directory protocol. If the memory block is not currently cached in the partial directory cache, the first memory access request is serviced using a directory-less protocol.

Abstract: Protocol agents involved in the performance of global coherency activity detect errors with respect to the activity being performed. The errors are logged by a computer system such that diagnostic software may be executed to determine the error detected and to trace the error to the erring software or hardware. In particular, information regarding the first error to be detected is logged. Subsequent errors may receive more or less logging depending upon programmable configuration values. Additionally, those errors which receive full logging may be programmably selected via error masks. The protocol agents each comprise multiple independent state machines which independently process requests. If the request which a particular state machine is processing results in an error, the particular state machine may enter a freeze state. Information regarding the request which is collected by the state machine may thereby be saved for later access.

Abstract: A symmetrical multiprocessing system includes a plurality of nodes interconnected by a hierarchical bus. To allow for the transfer of data between nodes and to restrict the global transfer of local transactions, a plurality of address partitions are defined: global space, local space, remote read space, and remote read and write space. Process private and local data is accessed using local space. Global data is accessed using global space. In one embodiment, a kernel of the operating system is resident in the local space of each node. Because the memory space where the kernel resides is designated as local space, no other nodes can write to, or corrupt, the node's kernel.

Abstract: A multiprocessing system having a plurality of processing nodes interconnected by an interconnect network. To optimize performance during spin-lock operations, a home agent prioritizes the servicing of read-to-own (RTO) transaction requests over the servicing of certain read-to-share (RTS) transaction requests, even if the RTO transaction requests are received by the processing node after receipt of the RTS transaction requests. In one implementation, this is accomplished by providing a first queue within the home agent for receiving RTO transaction requests conveyed via the interconnect network which is separate from a second queue for receiving RTS transaction requests. The queues may each be implemented with FIFO buffers.

Abstract: An apparatus for facilitating the sharing of memory blocks, which has local physical addresses at a computer node, between the computer node and an external device. The apparatus includes snooping logic configured for coupling with a common bus of the computer node. The snooping logic is configured to monitor, when coupled to the common bus, memory access requests on the common bus. There is also included a snoop tag array coupled to the snooping logic. The snoop tag array includes tags for tracking all copies of a first plurality of memory blocks of the memory blocks cached by the external device. Further, there is included a protocol transformer logic coupled to the snooping logic for enabling the apparatus, when coupled to the external device, to communicate with the external device using a protocol suitable for communicating with the external device.

Abstract: A computer system includes multiple local buses to which processors and other devices may be connected. A repeater is coupled to each of the local buses. Additionally, a top level repeater is coupled to each of the repeaters. The repeaters transmit transactions from the corresponding local buses to the top repeater. The top repeater, based upon the local or global nature of the transaction, transmits the transaction to one or more of the repeaters. The repeaters receiving the transaction then transmit the transaction upon the local buses attached thereto. If the transaction is a local transaction, the top repeater transmits the transaction to those repeaters which are configured into a local domain with the repeater which detected the initial transaction. The local domain comprises one or more repeaters which are logically interconnected. The local buses attached thereto logically form one SMP bus to which devices may be attached. Alternatively, the transaction may be a global transaction.

Abstract: A computer system defines a write transaction having a certain encoding as a prefetch command. A computer program developed for the computer system may include prefetch commands at points where the program has determined that a previously unreferenced coherency unit may be needed presently. By initiating the coherency activities for retrieving the coherency unit via a prefetch command, at least a portion of the latency inherent in that coherency activity may be experienced prior to executing an memory operation which accesses the coherency unit. In one embodiment, two prefetch commands are defined: a prefetch-shared command and a prefetch-modified command. The prefetch-shared command prefetches the coherency unit into the shared coherency state within the processing node which executes the prefetch command. On the other hand, the prefetch-modified command prefetches the coherency unit into the modified coherency state within the processing node which executes the prefetch command.

Abstract: A method, in a computer system having a first plurality of stored data objects and capable of running multiple threads concurrently, for preventing access conflicts. The method includes the step of providing a dynamic lock structure having a plurality of dynamic lock structure members. There is also the step of mapping a second plurality of stored data objects of the first plurality of stored data objects into a first dynamic lock structure member of the plurality of dynamic lock structure members in accordance with a mapping function. Due to the mapping function, the plurality of dynamic lock structure members become fewer in number than the number of the first plurality of stored data objects. The first dynamic lock structure member is configured to store identities of a third plurality of stored data objects.