Abstract: A processing device (60) for a radio-receiver circuit (20) is disclosed. The radio-receiver circuit comprises an input terminal (22) for receiving an analog input signal, circuitry (50) for generating a compensated analog input signal by subtracting an analog compensation signal from the analog input signal, an analog-to-digital converter (30) arranged to receive the compensated analog input signal on an input terminal of the analog-to-digital converter (30), and circuitry (40, 110) for to generating the analog compensation signal based on a digital compensation signal. The processing device (60) comprises: an input terminal (62) for receiving an output signal of the analog-to-digital converter (30); and an output terminal (64) for supplying the digital compensation signal.

Abstract: A device (10) for generating a digital output signal by digitizing an analog input signal is disclosed. The device (10) comprises a first signal path comprising a first ADC (20a) arranged to convert a first component of the analog input signal, residing in a first frequency band (40), to a first digital signal, and a second signal path comprising a second ADC (20b) arranged to convert a second component of the analog input signal, residing in a second frequency band (50), to a second digital signal. The first and the second frequency band (40, 50) overlap, such that there is a common frequency sub band (60), which is comprised in both the first and the second frequency band (40, 50). The device (10) comprises a combination unit (30).

Abstract: A device (10) for generating a digital output signal by digitizing an analog input signal is disclosed. The device (10) comprises a first signal path comprising a first ADC (20a) arranged to convert a first component of the analog input signal, residing in a first frequency band (40), to a first digital signal, and a second signal path comprising a second ADC (20b) arranged to convert a second component of the analog input signal, residing in a second frequency band (50), to a second digital signal. The first and the second frequency band (40, 50) overlap, such that there is a common frequency sub band (60), which is comprised in both the first and the second frequency band (40, 50). The device (10) comprises a combination unit (30).

Abstract: A processing device (60) for a radio-receiver circuit (20) is disclosed. The radio-receiver circuit comprises an input terminal (22) for receiving an analog input signal, circuitry (50) for generating a compensated analog input signal by subtracting an analog compensation signal from the analog input signal, an analog-to-digital converter (30) arranged to receive the compensated analog input signal on an input terminal of the analog-to-digital converter (30), and circuitry (40, 110) for to generating the analog compensation signal based on a digital compensation signal. The processing device (60) comprises: an input terminal (62) for receiving an output signal of the analog-to-digital converter (30); and an output terminal (64) for supplying the digital compensation signal.

Abstract: Implementations related to media playback and storage devices are presented herein.

Abstract: Implementations related to media playback and storage devices are presented herein.

Abstract: Methods, articles of manufacture and systems for the correction of static mismatch errors in D/A converters, where an input word, being the digital representation of an analog input signal, is divided into one most significant part, msb-word, and one least significant part, lsb-word, where msb-word is represented by msb-bits and lsb-word is represented by lsb-bits. Correction is performed by setting the effective weight of the least significant msb-bit to be less than the total sum of all lsb-bits, implementing a first look up table, LUT1, containing the most significant part of the error, so that a corrected msb-word, c-msb-word, would be equal to the msb-word plus a value in LUT1 representing the msb-word, and implementing a second look up table, LUT2, containing the least significant part of the error, so that a first corrected output, c1-output, would be equal to c-msb-word plus a value in LUT2 representing the c-msb-word added to the lsb-word.

Abstract: A driver circuit for powering an electronic device has a voltage source, two charge pump arrangements each having a diode connected in series with a capacitor. The charge pump arrangements are connected to the voltage source and the capacitors are charged, during a first phase, to a positive voltage level approximately equal to the voltage level of the voltage source. Furthermore, a switch is provided for switching the charge pump arrangements to a second phase, whereby they are charged simultaneously, one of the capacitors to a positive voltage approximately twice the voltage level provided by the voltage source and another one of the capacitors to a negative voltage level having a magnitude, which is approximately equal to a magnitude of the voltage source. An improved and cost-efficient driver circuit is thereby provided, having only few components.

Abstract: Methods, articles of manufacture and systems for the correction of static mismatch errors in D/A converters, where an input word, being the digital representation of an analog input signal, is divided into one most significant part, msb-word, and one least significant part, lsb-word, where msb-word is represented by msb-bits and lsb-word is represented by lsb-bits. Correction is performed by setting the effective weight of the least significant msb-bit to be less than the total sum of all lsb-bits, implementing a first look up table, LUT1, containing the most significant part of the error, so that a corrected msb-word, c-msb-word, would be equal to the msb-word plus a value in LUT1 representing the msb-word, and implementing a second look up table, LUT2, containing the least significant part of the error, so that a first corrected output, c1-output, would be equal to c-msb-word plus a value in LUT2 representing the c-msb-word added to the lsb-word.

Abstract: A switched-capacitor circuit includes a plurality of sequentially-operated switched-capacitors A first capacitor is arranged to be coupled and thereafter uncoupled to an input signal during a first time period. Thereby the first capacitor is charged to an input value in dependence on the input signal. A second capacitor is arranged to be coupled and thereafter uncoupled to the first capacitor during a second time period for charge distribution between the second and first capacitor. Pairwise charge distribution is possibly done with further sequentially-operated switched capacitors. A final capacitor is arranged to be coupled and thereafter uncoupled to a previous capacitor during the final time period for charge distribution between the final and the previous capacitor. The switched-capacitor circuit further includes selectively coupling the first and the second sequentially-operated switched-capacitors to an output circuit thereby enabling a desired weighting of the input signal to be attained.

Abstract: In a parallel Analog-to-Digital Converter (ADC) device a number of ADCS work in parallel, the conversion processes in each ADC overlapping the processes in the other ADCs. The number of ADCs and the sampling period at which samples arc taken and new conversion processes are periodically started in the ADCs are selected so that at each instant, at least one ADC is idling not performing any conversion. After the conversion is made by one of the ADCs, a choice is made whether the next sampled value is to be converted by this ADC or by the idling ADC. This choice can be made in a random or a pseudo-random way. Undesired tones existing in the composite output signal of parallel ADC devices having no such extra ADC are transferred to noise, as the error in the output signal caused by differences in the conversion characteristics of the ADCs is distributed in the frequency domain.

Abstract: The present invention relates to a method of offset compensating a parallel analogue-digital converter that includes at least two channels (35), where the analogue to digital conversion takes place simultaneously in the various channels but offset relative to respective channels. An analogue input signal (10) to the analogue-digital converter is multiplied by +1 or by −1 in accordance with an arbitrary pattern and the output signal from the analogue-digital converter is multiplied by +1 or by −1 in accordance with the same arbitrary pattern as that by which the input signal was multiplied. The invention also includes a parallel analogue-digital converter for carrying out the method.

Abstract: The present invention relates to a device for the input and processing of information comprising sensor elements arranged in matrix form, which are integrally formed on a substrate. Each sensor element comprises output electronics (3) and at least one photovoltaic cell (PD), which is adapted to convert an optical signal incident upon the photovoltaic cell to an electrical signal. The device according to the invention is characterized in that each sensor element is adapted to perform compensation of an offset error in the output electronics (3) forming part of the sensor element and that each sensor element is adapted to perform the said offset compensation independently of the other sensor elements in the device.

Abstract: An analog-to-digital converter (ADC) has a histogram based correction of static errors. In a control and calculating unit (23) of the converter thus the counts of uncorrected digital output codes are stored in a memory (51). From the stored counts a model distribution is determined in a calculation unit, e.g. by estimating an expected gaussian distribution. The model distribution is compared to the measured counts and relative errors of the counts are calculated, the relative errors indicating errors in coarse reference levels. The errors are used for calculating correction terms (L(A)) stored in a correction table (47). The correction terms are used by an output calculating unit (43′) to calculate corrected, more accurate output codes. For a parallel ADC device having several cells, the histograms in the cells can be used to correct for gain and offset errors. Also, the histogram can be used in a built-in self test.

Abstract: A process and device for providing an analog-to-digital conversion employing a successive approximation principle is provided. The search interval from a value X to a Value Y, which represents the value interval in which an unknown analog signal is to be converted to a digital signal value, is divided into a number of smaller search intervals, being divided into different area for employing a successive approximation process to iterate to the desired digital signal value. Further, reference levels are defined for each search interval to coincide with at least one other reference level, where coinciding reference level belongs to two search intervals formed by areas in a nearest larger search interval.

Abstract: A rotator comprises a gear housing which has a lower attachment for fitting the housing to the top of a mast, and which has extending therefrom a tube which can be rotated about its longitudinal axis relative to the gear housing by means of a gear therein, this tube being intended to carry a top sleeve, which in turn is intended to carry an aerial.

Abstract: Pipes for a telescopic mast have at least three guide grooves along their entire length, this is with the exception of the inner pipe having the smallest cross-sectional area which may not have guide grooves. All pipes except the pipe intended to be the outermost one in the telescopic mast have guide blocks attached to the lowermost portion of their outside. All pipes (4) except the pipe (4) intended to be the innermost one in the telescopic mast have guide blocks attached to the uppermost portion of their inside.

Abstract: A chlorinator for electrolytically producing chlorine from brine comprises an electrolytic cell having a vertical cation permeable diaphragm separating the anode and cathode compartments, a source of brine feeding concentrated brine into the anode compartment at regular intervals, and a mixing device in which chlorine gas produced by the electrolytic cell is mixed with a stream of water to be chlorinated. The electrolytic cell is provided with means for intermittently transferring small amounts of the anolyte from the anode compartment to the cathode compartment and for preventing the catholyte from coming into the anode compartment.