Abstract: The present invention provides methods and apparatus for reconfiguring protocol data for a multiplexed data stream which is reduced to carry fewer services for cable-side transmission in a cable television plant or the like. More particularly, the present invention provides methods and apparatus for reconfiguring protocol data for a desired combination of multiplexed data stream subgroups contained within an incoming high data rate data stream, such as a high data rate Quadrature Phase Shift Keying (QPSK) modulated multiplexed data stream, when the incoming multiplexed data stream is reduced.

Abstract: The present invention provides methods and apparatus for creating a Program Association Table (PAT) for a reduced portion of a multiplexed data stream, when the multiplexed data stream has been reduced, for example, to carry fewer services over a cable television plant. More particularly, the present invention provides methods and apparatus for creating a PAT for a desired combination of multiplexed data stream subgroups contained within an incoming data stream, when the incoming multiplexed data stream is reduced. The invention enables a new PAT to be output which correctly corresponds to the services in a reduced data stream (e.g., for cable-side transmissions). The present invention is particularly useful when reducing high data rate satellite television data streams for cable-side transmission.

Abstract: A method and apparatus for automatically detecting the format of a high-definition television (HDTV) signal at a video encoder to allow proper encoding of the signal, including progressive and interlaced scan, and specific pixel and vertical line resolutions. The system is compatible with video standards such as the SMPTE and MPEG-2 standards. A video sample clock is determined by phase-locking clock pulses in a video signal to one of two or more available reference clocks. An SAV/EAV counter and pixel sample counter determine the horizontal resolution of the video, e.g., pixels per line. The system discriminates between 24 frames per second video and 30 frames per second video, and between a 720 line progressive scan signal and a 1080 line interlaced scan signal, for example. The system uses PLLs for each reference clock, where a lock range of the PLLs is narrow such that two PLLs will not lock at the same time for one input frequency.