Abstract: An integrated platform system that employ a series of machine learning techniques and prediction and detection units that can process input data and extract and generate meaningful insights and predictions therefrom. The system integrates together multiple different data storage types and applications that generates data of different types, and an associated processing system for processing the different data types, store the data in a common data model to normalize the data, determine the data lineage of the data, and then process the data using different types of techniques. The data can also be processed by a prediction unit for generating meaningful insights and predictions or by an anomaly detection unit for detecting one or more anomalies in the data.

Abstract: An integrated platform system that employ a series of machine learning techniques and prediction and detection units that can process input data and extract and generate meaningful insights and predictions therefrom. The system integrates together multiple different data storage types and applications that generates data of different types, and an associated processing system for processing the different data types, store the data in a common data model to normalize the data, determine the data lineage of the data, and then process the data using different types of techniques. The data can also be processed by a prediction unit for generating meaningful insights and predictions or by an anomaly detection unit for detecting one or more anomalies in the data.

Abstract: A data management method for a processor to which a first cache, a second cache, and a behavior history table are allocated, includes tracking reuse information learning cache lines stored in at least one of the first cache and the second cache; recording the reuse information in the behavior history table; and determining a placement policy with respect to future operations that are to be performed on a plurality of cache lines stored in the first cache and the second cache, based on the reuse information in the behavior history table.

Abstract: A multiprocessor system includes a plurality of nodes and at least one memory, each node containing at least one processor; a first cache configured to store a plurality of first cache lines, the first cache being private to at least one node from among the plurality of nodes; and a second cache configured to store a plurality of second cache lines, the second cache being at a higher level than the first cache, wherein at least one of the first cache lines includes a first associated pointer pointing to a location of one of the second cache lines, and wherein at least one of the second cache lines includes a second associated pointer pointing to a location of one of the first cache lines.

Abstract: Caches may be vulnerable to side-channel attacks, such as Spectre and Meltdown, that involve speculative execution of instructions, revealing information about a cache that the attacker is not permitted to access. Access permission may be stored in the cache, such as in an entry of a cache table or in the region information for a cache table. Optionally, the access permission may be re-checked if the access permission changes while a memory instruction is pending. Optionally, a random index value may be stored in a cache and used, at least in part, to identify a memory location of a cacheline. Optionally, cachelines that are involved in speculative loads for memory instructions may be marked as speculative. On condition of resolving the speculative load as non-speculative, the cacheline may be marked as non-speculative; and on condition of resolving the speculative load as mis-speculated, the cacheline may be removed from the cache.

Abstract: A data management method for a computer system including at least one processor and at least a first cache, a second cache, a victim buffer (VB), and a memory allocated to the at least one processor, includes selecting a victim cache line to be evicted from the first cache; finding a VB location corresponding to the victim cache line from a set of the VB; copying data of the victim cache line to a data field of the VB location; copying a backward pointer (BP) associated with the victim cache line to a BP field of the VB location; and reclaiming victim space of the first cache using the VB.

Abstract: A multiprocessor system includes a plurality of nodes and at least one memory, wherein each node includes at least one processor, a first cache private to the node, a second cache at a higher level than the first cache, and a cache location buffer (CLB) private to the node, wherein, for at least one node of the plurality of nodes, at least one of the first cache and the second cache included in the at least one node includes at least one cache location that is capable of storing a compressed data unit of varying size, the CLB included in the at least one node is configured to store a plurality of CLB entries, each of the CLB entries including a plurality of location information values.

Abstract: Caches may be vulnerable to side-channel attacks, such as Spectre and Meltdown, that involve speculative execution of instructions, revealing information about a cache that the attacker is not permitted to access. Access permission may be stored in the cache, such as in an entry of a cache table or in the region information for a cache table. Optionally, the access permission may be re-checked if the access permission changes while a memory instruction is pending. Optionally, a random index value may be stored in a cache and used, at least in part, to identify a memory location of a cacheline. Optionally, cachelines that are involved in speculative loads for memory instructions may be marked as speculative. On condition of resolving the speculative load as non-speculative, the cacheline may be marked as non-speculative; and on condition of resolving the speculative load as mis-speculated, the cacheline may be removed from the cache.

Abstract: A multiprocessor system includes a plurality of nodes and at least one memory, wherein each node includes at least one processor, a first cache private to the node, a second cache at a higher level than the first cache, and a cache location buffer (CLB) private to the node, wherein, for at least one node of the plurality of nodes, at least one of the first cache and the second cache included in the at least one node includes at least one cache location that is capable of storing a compressed data unit of varying size, the CLB included in the at least one node is configured to store a plurality of CLB entries, each of the CLB entries including a plurality of location information values.

Abstract: A data management method for a computer system including at least one processor and at least a first cache, a second cache, a victim buffer (VB), and a memory allocated to the at least one processor, includes selecting a victim cache line to be evicted from the first cache; finding a VB location corresponding to the victim cache line from a set of the VB; copying data of the victim cache line to a data field of the VB location; copying a backward pointer (BP) associated with the victim cache line to a BP field of the VB location; and reclaiming victim space of the first cache using the VB.

Abstract: A data management method for a processor to which a first cache, a second cache, and a behavior history table are allocated, includes tracking reuse information learning cache lines stored in at least one of the first cache and the second cache; recording the reuse information in the behavior history table; and determining a placement policy with respect to future operations that are to be performed on a plurality of cache lines stored in the first cache and the second cache, based on the reuse information in the behavior history table.

Abstract: A multiprocessor system includes a plurality of nodes and at least one memory, each node containing at least one processor; a first cache configured to store a plurality of first cache lines, the first cache being private to at least one node from among the plurality of nodes; and a second cache configured to store a plurality of second cache lines, the second cache being at a higher level than the first cache, wherein at least one of the first cache lines includes a first associated pointer pointing to a location of one of the second cache lines, and wherein at least one of the second cache lines includes a second associated pointer pointing to a location of one of the first cache lines.

Abstract: A system image customization tool provides an efficient and cost effective way to implement a highly customizable system image for a digital device. The system image customization tool controls application installation, device settings, and selection, delivery methods and licensing options for products, applications and services with minimal or no customer interaction from the customer's first out of box experience with the device and through the lifecycle use of the device. The system image customization tool provides retailers, original equipment manufacturers and products, applications and services providers a way to create new distribution channels and partnerships.

Abstract: A system image customization tool provides an efficient and cost effective way to implement a highly customizable system image for a digital device. The system image customization tool controls application installation, device settings, and selection, delivery methods and licensing options for products, applications and services with minimal or no customer interaction from the customer's first out of box experience with the device and through the lifecycle use of the device. The system image customization tool provides retailers, original equipment manufacturers and products, applications and services providers a way to create new distribution channels and partnerships.

Abstract: A device for detecting the depth of penetration of the tip of an indenter of a hardness tester has a terminal crown turnable and slantable with respect to a cylindrical body of a reference sleeve, terminating with two spikes extending from diametrically opposed positions of a circular end surface of the terminal crown, the vertexes of which bear on the surface of the piece to be tested. The terminal crown having an end retained within the body of the sleeve and an inner circular surface defining a cuspid along a diameter orthogonal to the diameter of alignment of said two spikes, abutting on a planar circular end surface of the retaining body of the sleeve such to determine a linear or fulcrum abutment along diametrically aligned vertexes of said cuspid. The tester uses an indenter of a hard metal or compound by periodically recalibrating a hardness tester in function of said depth of penetration originally established on a reference sample of known and homogenous hardness.