Patents by Inventor Erik G. Hallnor
Erik G. Hallnor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10705961Abstract: A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored.Type: GrantFiled: September 27, 2013Date of Patent: July 7, 2020Assignee: Intel CorporationInventors: Yen-Cheng Liu, Bahaa Fahim, Erik G. Hallnor, Jeffrey D. Chamberlain, Stephen R. Van Doren, Antonio Juan
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Patent number: 9954792Abstract: Traffic control logic is provided to support a plurality of channels on a link. A plurality of reserved credit counters is provided to each identify reserved flow control credits for a corresponding one of the plurality of channels. Further, a shared credit counter is provided to identify shared flow control credits to be shared between two or more of the plurality of virtual channels.Type: GrantFiled: December 20, 2014Date of Patent: April 24, 2018Assignee: Intel CorporationInventors: Kevin B. Theobald, Rupin H. Vakharwala, Robert J. Toepfer, Erik G. Hallnor, Robert P. Adler
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Patent number: 9785223Abstract: In an example, a shared uncore memory fabric of a system-on-a-chip (SoC) is configured to provide real-time power management. The SoC may include a power management agent to inform the shared fabric that the processing cores and peripherals will be idle for a time, and to negotiate a power-saving state. The uncore fabric may also include a local power manager that detects when no access requests have been received for a time, such as when cores are operating from cache. The shared fabric may then unilaterally enter a power-saving state, and remain in that state until an access request is received. In the power-saving state, power and/or clocks are gated, and the fabric's state is stored in retention cells. When a new access request is received, an ungated controller may handle preliminary processing while the local power manager restores the state and powers up the shared fabric.Type: GrantFiled: December 25, 2014Date of Patent: October 10, 2017Assignee: Intel CorporationInventors: Ramadass Nagarajan, Jeremy J. Shrall, Erik G. Hallnor, Vinit Mathew Abraham, Ezra N. Harrington
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Patent number: 9710041Abstract: In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.Type: GrantFiled: July 29, 2015Date of Patent: July 18, 2017Assignee: Intel CorporationInventors: Alexander Gendler, Larisa Novakovsky, Krishnakanth V. Sistla, Vivek Garg, Dean Mulla, Ashish V. Choubal, Erik G. Hallnor, Kimberly C. Weier
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Publication number: 20170031412Abstract: In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.Type: ApplicationFiled: July 29, 2015Publication date: February 2, 2017Inventors: Alexander Gendler, Larisa Novakovsky, Krishnakanth V. Sistla, Vivek Garg, Dean Mulla, Ashish V. Choubal, Erik G. Hallnor, Kimberly C. Weier
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Publication number: 20160283232Abstract: A processor includes a core and a prefetcher. The prefetcher includes logic to issue a request for data including a requested prefetch. The core includes logic to receive an indication of the request, determine whether the request is for a restricted region of memory, and, based upon whether the request is for the restricted region of memory, allow or deny the request.Type: ApplicationFiled: March 27, 2015Publication date: September 29, 2016Inventors: Raanan Sade, Ryan L. Carlson, Larisa Novakovsky, Erik G. Hallnor, Ravi Rajwar, Roman Dementiev
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Publication number: 20160187959Abstract: In an example, a shared uncore memory fabric of a system-on-a-chip (SoC) is configured to provide real-time power management. The SoC may include a power management agent to inform the shared fabric that the processing cores and peripherals will be idle for a time, and to negotiate a power-saving state. The uncore fabric may also include a local power manager that detects when no access requests have been received for a time, such as when cores are operating from cache. The shared fabric may then unilaterally enter a power-saving state, and remain in that state until an access request is received. In the power-saving state, power and/or clocks are gated, and the fabric's state is stored in retention cells. When a new access request is received, an ungated controller may handle preliminary processing while the local power manager restores the state and powers up the shared fabric.Type: ApplicationFiled: December 25, 2014Publication date: June 30, 2016Inventors: Ramadass Nagarajan, Jeremy J. Shrall, Erik G. Hallnor, Vinit Mathew Abraham, Ezra N. Harrington
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Publication number: 20160188503Abstract: In an example, a system on chip (SoC) includes virtual legacy wire (VLW) functionality. The VLW signal virtualizes a physical interrupt existing in legacy systems to enable a peripheral to cause a processor to enter an interrupt handling routine relevant to the peripheral. The VLW interrupt is broadcast to all cores or agents within the SoC. However, to save power, if one or more agents are asleep when the interrupt occurs, the agents are not awakened to receive the interrupt. Rather, the VLW is broadcast with a mask to exclude those agents, and the state of those agents is stored in a register or buffer. Once a power management agent notifies the VLW broadcaster that an agent has newly awakened. The VLW interrupt is then re-broadcast, with a mask that excludes all but the newly-awakened agent.Type: ApplicationFiled: December 25, 2014Publication date: June 30, 2016Inventor: Erik G. Hallnor
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Publication number: 20160182391Abstract: Traffic control logic is provided to support a plurality of channels on a link. A plurality of reserved credit counters is provided to each identify reserved flow control credits for a corresponding one of the plurality of channels. Further, a shared credit counter is provided to identify shared flow control credits to be shared between two or more of the plurality of virtual channels.Type: ApplicationFiled: December 20, 2014Publication date: June 23, 2016Inventors: Kevin B. Theobald, Rupin H. Vakharwala, Robert J. Toepfer, Erik G. Hallnor, Robert P. Adler
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Patent number: 9336156Abstract: A processing device and method for cache control including tracking updates to the line state of a cache superline are described. In response to a request pertaining to a superline, a cache controller of the processing device can perform one or more read-modify-write (RMW) operations to (a) a line state vector of a line state array and (b) a counter of the line state array. Based on a determination that one or more requests to the superline have completed, the line state vector from the line state array can be written to a tag array. The cache controller can track pending line state updates to a superline outside of the tag array, and a line state update can occur in the cache controller, rather than awaiting completion of all outstanding operations on a superline. Updates to multiple line states can be maintained simultaneously, and up-to-date ECCs computed.Type: GrantFiled: March 14, 2013Date of Patent: May 10, 2016Assignee: Intel CorporationInventors: Zhongying Zhang, Erik G. Hallnor, Stanley S. Kulick, Jeffrey L. Miller
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Publication number: 20150095580Abstract: A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Inventors: Yen-Cheng Liu, Bahaa Fahim, Erik G. Hallnor, Jeffrey D. Chamberlain, Stephen R. Van Doren, Antonio Juan
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Publication number: 20140281251Abstract: Technologies for tracking updates to the line state of a cache superline are described. In response to a request pertaining to a superline, one or more read-modify-write (RMW) operations to (a) a line state vector of a line state array and (b) a counter of the line state array can be performed. Based on a determination that one or more requests to the superline have completed, the line state vector from the line state array can be written to a tag array.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: Zhongying Zhang, Erik G. Hallnor, Stanley S. Kulick, Jeffrey L. Miller
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Patent number: 8392657Abstract: An apparatus, method, and system are disclosed. In one embodiment the apparatus includes a cache memory, which a number of sets. Each of the sets in the cache memory have several cache lines. The apparatus also includes at least one process resource table. The process resource table maintains a cache line occupancy count of a number of cache lines. Specifically, the cache line occupancy count for each cache line describes the number of cache lines in the cache storing information utilized by a process running on a computer system. Additionally, the process resource table stores the occupancy count of less cache lines than the total number of cache lines in the cache memory.Type: GrantFiled: October 9, 2009Date of Patent: March 5, 2013Assignee: Intel CorporationInventors: Li Zhao, Ravishankar Iyer, Rameshkumar G. Illikkal, Erik G. Hallnor, Martin G. Dixon, Donald K. Newell
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Patent number: 8316184Abstract: Domain-based cache management methods and systems, including domain event based priority demotion (“EPD”). In EPD, priorities of cached data blocks are demoted upon one or more domain events, such as upon encoding of one or more macroblocks of a video frame. New data blocks may be written over lowest priority cached data blocks. New data blocks may initially be assigned a highest priority. Alternatively, or additionally, one or more new data blocks may initially be assigned one of a plurality of higher priorities based on domain-based information, such as a relative position of a requested data block within a video frame, and/or a relative direction associated with a requested data block. Domain-based cache management may be implemented with one or more other cache management techniques, such as least recently used techniques. Domain-based cache management may be implemented in associative caches, including set associative caches and fully associative caches, and may be implemented with indirect indexing.Type: GrantFiled: June 30, 2008Date of Patent: November 20, 2012Assignee: Intel CorporationInventors: Zhen Fang, Erik G Hallnor, Nitin B Gupte, Steven Zhang
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Patent number: 8090967Abstract: A proposal for power management control of an interconnect structure based on power state transition control. The power state transition is based on generating early warning signals and an idle timeout value setting based on response time and detection of subsequent requests.Type: GrantFiled: May 23, 2008Date of Patent: January 3, 2012Assignee: Intel CorporationInventors: Erik G. Hallnor, Zhen Fang, Hemant G. Rotithor
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Publication number: 20110087843Abstract: An apparatus, method, and system are disclosed. In one embodiment the apparatus includes a cache memory, which a number of sets. Each of the sets in the cache memory have several cache lines. The apparatus also includes at least one process resource table. The process resource table maintains a cache line occupancy count of a number of cache lines. Specifically, the cache line occupancy count for each cache line describes the number of cache lines in the cache storing information utilized by a process running on a computer system. Additionally, the process resource table stores the occupancy count of less cache lines than the total number of cache lines in the cache memory.Type: ApplicationFiled: October 9, 2009Publication date: April 14, 2011Inventors: Li Zhao, Ravishankar Iyer, Rameshkumar G. Illikkal, Erik G. Hallnor, Martin G. Dixon, Donald K. Newell
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Publication number: 20090327611Abstract: Domain-based cache management methods and systems, including domain event based priority demotion (“EPD”). In EPD, priorities of cached data blocks are demoted upon one or more domain events, such as upon encoding of one or more macroblocks of a video frame. New data blocks may be written over lowest priority cached data blocks. New data blocks may initially be assigned a highest priority. Alternatively, or additionally, one or more new data blocks may initially be assigned one of a plurality of higher priorities based on domain-based information, such as a relative position of a requested data block within a video frame, and/or a relative direction associated with a requested data block. Domain-based cache management may be implemented with one or more other cache management techniques, such as least recently used techniques. Domain-based cache management may be implemented in associative caches, including set associative caches and fully associative caches, and may be implemented with indirect indexing.Type: ApplicationFiled: June 30, 2008Publication date: December 31, 2009Inventors: Zhen Fang, Erik G. Hallnor, Nitin B. Gupte, Steven Zhang
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Publication number: 20090292935Abstract: A proposal for power management control of an interconnect structure based on power state transition control. The power state transition is based on generating early warning signals and an idle timeout value setting based on response time and detection of subsequent requests.Type: ApplicationFiled: May 23, 2008Publication date: November 26, 2009Inventors: Erik G. Hallnor, Zhen Fang, Hemant G. Rotithor