Patents by Inventor Erik Geiss
Erik Geiss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10707175Abstract: One illustrative example of an overlay mark disclosed herein includes four quadrants (I-IV). Each quadrant of the mark contains an inner periodic structure and an outer periodic structure. Each of the outer periodic structures includes a plurality of outer features. Each of the inner periodic structures includes a plurality of first inner groups, each of the first inner groups having a plurality of first inner features, each first inner group being oriented such that there is an end-to-end spacing relationship between each first inner group and a selected one of the outer features.Type: GrantFiled: May 22, 2018Date of Patent: July 7, 2020Assignee: GLOBALFOUNDRIES Inc.Inventors: Wei Zhao, Minghao Tang, Rui Chen, Dongyue Yang, Haiting Wang, Erik Geiss, Scott Beasor
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Publication number: 20190363053Abstract: One illustrative example of an overlay mark disclosed herein includes four quadrants (I-IV). Each quadrant of the mark contains an inner periodic structure and an outer periodic structure. Each of the outer periodic structures includes a plurality of outer features. Each of the inner periodic structures includes a plurality of first inner groups, each of the first inner groups having a plurality of first inner features, each first inner group being oriented such that there is an end-to-end spacing relationship between each first inner group and a selected one of the outer features.Type: ApplicationFiled: May 22, 2018Publication date: November 28, 2019Inventors: Wei Zhao, Minghao Tang, Rui Chen, Dongyue Yang, Haiting Wang, Erik Geiss, Scott Beasor
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Patent number: 10475890Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.Type: GrantFiled: October 9, 2017Date of Patent: November 12, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Haiting Wang, Wei Zhao, Hui Zang, Hong Yu, Zhenyu Hu, Scott Beasor, Erik Geiss, Jerome Ciavatti, Jae Gon Lee
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Publication number: 20190109197Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.Type: ApplicationFiled: October 9, 2017Publication date: April 11, 2019Inventors: Haiting WANG, Wei ZHAO, Hui ZANG, Hong YU, Zhenyu HU, Scott BEASOR, Erik GEISS, Jerome CIAVATTI, Jae Gon LEE
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Patent number: 9397004Abstract: A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings.Type: GrantFiled: January 27, 2014Date of Patent: July 19, 2016Assignee: GLOBALFOUNDRIES, INC.Inventors: Guillaume Bouche, Erik Geiss, Scott Beasor, Andy Wei, Deniz Elizabeth Civay
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Publication number: 20150214113Abstract: A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings.Type: ApplicationFiled: January 27, 2014Publication date: July 30, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Guillaume Bouche, Erik Geiss, Scott Beasor, Andy Wei, Deniz Elizabeth Civay
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Patent number: 8927407Abstract: Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.Type: GrantFiled: January 20, 2012Date of Patent: January 6, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Peter Baars, Andy Wei, Erik Geiss, Martin Mazur
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Patent number: 8614123Abstract: Disclosed herein are various methods of forming a semiconductor device using sacrificial gate electrodes and sacrificial self-aligned contacts. In one example, the method includes forming two spaced-apart sacrificial gate electrodes comprised of a first material, forming a sacrificial contact structure comprised of a second material, wherein the second material is selectively etchable with respect to said first material, and performing an etching process on the two spaced-apart sacrificial gate electrodes and the sacrificial contact structure to selectively remove the two spaced-apart sacrificial gate electrode structures selectively relative to the sacrificial contact structure.Type: GrantFiled: November 28, 2011Date of Patent: December 24, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Andy Wei, Peter Baars, Erik Geiss
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Publication number: 20130189833Abstract: Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.Type: ApplicationFiled: January 20, 2012Publication date: July 25, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Peter Baars, Andy Wei, Erik Geiss, Martin Mazur
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Publication number: 20130137257Abstract: Disclosed herein are various methods of forming a semiconductor device using sacrificial gate electrodes and sacrificial self-aligned contacts. In one example, the method includes forming two spaced-apart sacrificial gate electrodes comprised of a first material, forming a sacrificial contact structure comprised of a second material, wherein the second material is selectively etchable with respect to said first material, and performing an etching process on the two spaced-apart sacrificial gate electrodes and the sacrificial contact structure to selectively remove the two spaced-apart sacrificial gate electrode structures selectively relative to the sacrificial contact structure.Type: ApplicationFiled: November 28, 2011Publication date: May 30, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Andy Wei, Peter Baars, Erik Geiss
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Patent number: 7601641Abstract: Methods are provided for etching during fabrication of a semiconductor device. The method includes initially etching to partially remove a portion of one or more lithographic-aiding layers overlying an oxide layer while etching a first portion of the oxide layer in accordance with a mask formed by the one or more lithographic-aiding layers, and thereafter additionally etching to remove remaining portions of the one or more lithographic-aiding layers while etching a remaining portion of the oxide layer.Type: GrantFiled: March 31, 2008Date of Patent: October 13, 2009Assignee: Global Foundries, Inc.Inventors: Erik Geiss, Christopher Prindle, Sven Beyer
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Publication number: 20090246959Abstract: Methods are provided for etching during fabrication of a semiconductor device. The method includes initially etching to partially remove a portion of one or more lithographic-aiding layers overlying an oxide layer while etching a first portion of the oxide layer in accordance with a mask formed by the one or more lithographic-aiding layers, and thereafter additionally etching to remove remaining portions of the one or more lithographic-aiding layers while etching a remaining portion of the oxide layer.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Erik GEISS, Christopher PRINDLE, Sven BEYER