Abstract: A chip-based prober for measuring a device-under-test is provided. The prober includes a probe tip, a voltage and control connector, a chip carrier, and a programmable termination chip. The probe tip is configured to contact the device-under-test. The voltage and control connector is in electrical communication with the probe tip. The programmable termination chip has a plurality of terminations interconnected with the voltage and control connector and the chip carrier through controlled collapsed chip connections.

Abstract: A chip-based prober for measuring a device-under-test is provided. The prober includes a probe tip, a voltage and control connector, a chip carrier, and a programmable termination chip. The probe tip is configured to contact the device-under-test. The voltage and control connector is in electrical communication with the probe tip. The programmable termination chip has a plurality of terminations interconnected with the voltage and control connector and the chip carrier through controlled collapsed chip connections.

Abstract: A chip-based prober for measuring a device-under-test is provided. The prober includes a probe tip, a voltage and control connector, a chip carrier, and a programmable termination chip. The probe tip is configured to contact the device-under-test. The voltage and control connector is in electrical communication with the probe tip. The programmable termination chip has a plurality of terminations interconnected with the voltage and control connector and the chip carrier through controlled collapsed chip connections.

Abstract: A technique for simplifying a structure so that subsequent electrical analysis can be more efficiently performed. The technique includes facility to modify the existing shapes in the structure so that they do not overlap, to determine the allowed movement of each edge of each shape in the structure, to apply a set of factors to each movement that determines how advantageous the movement is with respect to the number of unknowns and the change in geometry and/or electrical parameters of the structure, and to choose and then make the movement associated with the highest factor. The factors are unity based so that the desirability of the move is given by the product of all the factors. The technique includes facility to iterate, calculating the factors and making the movement associated with the greatest factor, until the factor falls below a given threshold. The resulting structure will be similar in electrical characteristics to the original structure, yet require fewer unknowns to analyze.

Abstract: A technique for simplifying a structure so that subsequent electrical analysis can be more efficiently performed. The technique includes facility to modify the existing shapes in the structure so that they do not overlap, to determine the allowed movement of each edge of each shape in the structure, to apply a set of factors to each movement that determines how advantageous the movement is with respect to the number of unknowns and the change in geometry and/or electrical parameters of the structure, and to choose and then make the movement associated with the highest factor. The factors are unity based so that the desirability of the move is given by the product of all the factors. The technique includes facility to iterate, calculating the factors and making the movement associated with the greatest factor, until the factor falls below a given threshold. The resulting structure will be similar in electrical characteristics to the original structure, yet require fewer unknowns to analyze.