Abstract: An integrated circuit (10) comprises a functional circuit (12a-c) that contain information that must be secured against unauthorized access. The integrated circuit comprises a test access circuit (14, 16) coupled to the functional circuit (12a-c), and a plurality of fuse elements (18) coupled to the test access circuit (14, 16). The fuse elements (18) are connected in a circuit configuration that makes the functional circuit (12a-c) consistently accessible via the test access circuit (14, 16) only when first fuse elements (18) of the plurality are in a blown state and second fuse elements (18) of the plurality are in a not-blown state. As a result the integrated circuit can be tested after selectively blowing all of the first fuse elements (18). After testing at least part of the second fuse elements (18) is blown.

Abstract: An integrated circuit comprises a scan chain with parallel inputs and outputs coupled to a functional circuit. A scan chain modifying circuit is provided coupled to the scan chain. When testing is authorized the scan chain modifying circuit operates in a mode wherein a normal shift path is provided through the scan chain. When testing is not authorized the scan chain modifying circuit operates to effect spontaneous dynamic changes in the shift path, which dynamically vary the length of the shift path between external terminals of the integrated circuit while shifting takes place. In an embodiment the dynamical variations are controlled by a running key comparison. In other embodiments running key comparison is used to disable transfer through the scan chain or operation of functional circuits.

Abstract: According to an example embodiment of the present invention, there is a test access architecture for testing modules in an electronic circuit. The test access architecture includes a test access mechanism (TAM) having a plurality of modules connected in series thereto; the test access mechanism is arranged to transport test stimulus data to, and test response data from a module being tested. A global enable signal is provided for placing the modules in a test mode. A control circuit is provided between the global enable signal and an associated module; wherein the control circuit is arranged to control whether or not the global enable signal is passed to its associated module.

Abstract: A memory array, and in particular, an embedded memory array is tested by interfacing to a stimulus generator and a response evaluator pair. In a non-test condition the pair is steered in a transparent mode, and in a test condition in a stimulus generating mode and a response evaluating mode respectively. In a subsequent array repair condition row and/or column-based repair intervention are allowed. In particular, the evaluator will evaluate correspondence between successive fault patterns, and further in a fault response signalizing mode to external circuitry on the basis of a predetermined correspondence between an earlier fault pattern and a later fault pattern signalize one of the two compared patterns only in the form of a lossless compressed response pattern.

Abstract: The method for modifying a representation of a digital circuit (102) in order to allow a scan test comprises a step (106) for selecting a number of the memory elements of the circuit to be made scannable. In this step it is determined whether the circuit comprises a redundant structure. In case of a sequentially redundant structure (200), a memory element (214,216,218,220) of this structure is selected to be made scannable thus providing a pseudo input to the structure and removing the redundancy during scan test. In case of a combinational redundant structure (406), a memory element (404) connecting this structure to another part of the circuit is selected to be made scannable, thus avoiding the propagation of the redundancy of the structure.

Abstract: A integrated circuit (100) includes a plurality of cores (110, 120). With each core (110, 120) is associated a TCB (112, 122) for controlling the core in a test mode thereof. Each TCB has a shift register (220) for holding test control data. The TCBs (112, 122) are serially linked in a chain (140) so that, the test control data can be serially shifted in. A system TCB (130) is provided in the chain (140) comprising a further shift register (220). The system TCB (130) is connected to each TCB (112, 122) for, after receiving a particular set of test control data in its shift register (220), providing the TCBs (112, 122) with a system test hold signal for switching between a shift mode and an application mode of the TCBs (112, 122).