Patents by Inventor Erik J. Roggeman

Erik J. Roggeman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6992389
    Abstract: A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: January 31, 2006
    Assignee: International Business Machines Corporation
    Inventors: Panayotis C. Andricacos, Tien-Jen J. Cheng, Emanuel I. Cooper, David E. Eichstadt, Jonathan H. Griffith, Randolph F. Knarr, Roger A. Quon, Erik J. Roggeman
  • Patent number: 6622907
    Abstract: Start with a semiconductor substrate with contacts exposed through an insulating layer. Form a base over the contacts, with the base composed of at least one metal layer. Then form a conductive metal layer over the base. Form a mask over the top surface of the conductive metal layer with C4 solder bump openings therethrough with the shape of C4 solder bump images down to the surface of the conductive metal layer above the contacts. Etch away the exposed portions of the conductive metal layer below the C4 solder bump openings to form through holes in the conductive metal layer exposing C4 solder bump plating sites on the top surface of the base below the C4 solder bump openings with the conductive metal layer remaining intact on the periphery of the through holes at the C4 solder bump plating sites. As an option, form a barrier layer over the plating sites next.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: September 23, 2003
    Assignee: International Business Machines Corporation
    Inventors: Lisa A. Fanti, Randolph F. Knarr, Erik J. Roggeman, Kamalesh K. Srivastava
  • Publication number: 20030155408
    Abstract: Start with a semiconductor substrate with contacts exposed through an insulating layer. Form a base over the contacts, with the base composed of at least one metal layer. Then form a conductive metal layer over the base. Form a mask over the top surface of the conductive metal layer with C4 solder bump openings therethrough with the shape of C4 solder bump images down to the surface of the conductive metal layer above the contacts. Etch away the exposed portions of the conductive metal layer below the C4 solder bump openings to form through holes in the conductive metal layer exposing C4 solder bump plating sites on the top surface of the base below the C4 solder bump openings with the conductive metal layer remaining intact on the periphery of the through holes at the C4 solder bump plating sites. As an option, form a barrier layer over the plating sites next.
    Type: Application
    Filed: February 19, 2002
    Publication date: August 21, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lisa A. Fanti, Randolph F. Knarr, Erik J. Roggeman, Kamalesh K. Srivastava