Patents by Inventor Erik Jan Marinissen
Erik Jan Marinissen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9678142Abstract: The present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer. In one aspect, a method for testing an interconnect in a semiconductor die comprises providing the semiconductor die, which includes a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die, at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, and an electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element.Type: GrantFiled: April 7, 2014Date of Patent: June 13, 2017Assignee: IMECInventors: Julien Ryckaert, Erik Jan Marinissen, Dimitri Linten
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Patent number: 9568536Abstract: A test circuitry is configured to test for transition delay defects in a first inter-die interconnect connecting a first die and a second die. A test data value is initially received and temporarily stored in a data storage element. The test data is subsequently looped between the storage element and the second die through a feedback loop including the first inter-die interconnect and a second inter-die interconnect. A data conditioner conditions the test data value received from the second die so as to make it distinguishable from the test data value sent to the second die. A clock pulse generator generates a delayed clock pulse. A selection logic applies the generated delayed clock pulse and the conditioned fed back test data value to the data storage element. A readout unit for reading out a test data value stored in the data storage element.Type: GrantFiled: October 21, 2013Date of Patent: February 14, 2017Assignees: IMEC, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sandeep Kumar Goel, Erik Jan Marinissen
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Patent number: 9239359Abstract: A test access architecture is disclosed for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.Type: GrantFiled: September 25, 2012Date of Patent: January 19, 2016Assignees: IMEC, Stichting IMEC NederlandInventors: Erik Jan Marinissen, Jacobus Verbree, Mario Konijnenburg, Chun-Chuan Chi
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Patent number: 8914689Abstract: A method is provided to test a modular integrated circuit (IC) comprising: testing a module-under-test (MUT) within the IC while causing a controlled toggle rate within a first neighbor module of the MUT; wherein the controlled toggle rate within the first neighbor module is selected so that toggling within the first neighbor module has substantially the same effect upon operation of the MUT that operation of the first neighbor module would have during actual normal functional operation of the first neighbor module.Type: GrantFiled: September 14, 2012Date of Patent: December 16, 2014Assignees: Cadence Design Systems, Inc., IMECInventors: Erik Jan Marinissen, Sergej Deutsch
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Publication number: 20140300379Abstract: The present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer. In one aspect, a method for testing an interconnect in a semiconductor die comprises providing the semiconductor die, which includes a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die, at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, and an electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element.Type: ApplicationFiled: April 7, 2014Publication date: October 9, 2014Applicant: IMECInventors: Julien RYCKAERT, Erik Jan MARINISSEN, Dimitri LINTEN
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Patent number: 8773157Abstract: A test circuit and method for testing through-silicon-vias (TSVs) in three-dimensional integrated circuits (ICs) during each phase of manufacturing is disclosed. In one aspect, the method includes testing for faults in each individual TSV, TSV-under-test, shorts between a TSV-under-test, and TSVs in close proximity and for connections between the TSV-under-test and another tier in the ICs. A test circuit has three switchable current paths connected to a power supply via a pull-up resistor and switches: a calibration path, a short path, and a current measurement path. A power supply is connected to the measurement path, and the calibration path and the short path are connected to ground via respective pull-down resistors. For each TSV-under-test, the desired operation mode is selected by the closure of different combinations of switches. The current flowing through the pull-up resistor in each operation mode indicates whether the TSV-under-test has passed or failed the test.Type: GrantFiled: June 30, 2011Date of Patent: July 8, 2014Assignee: IMECInventors: Mustafa Badaroglu, Erik Jan Marinissen, Paul Marchal
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Publication number: 20140111243Abstract: A test circuitry configured to test for transition delay defects in inter-die interconnects is disclosed. In one aspect, the test circuitry comprises an input port configured to receive a test data value and a data storage element configured to temporarily store the test data value. The test circuitry additionally comprises a second inter-die interconnect configured to be electrically connected to a first inter-die interconnect so as to form a feedback loop for transferring the test data value from the data storage element back to the data storage element. The test circuitry additionally comprises a data conditioner configured to condition the fed back test data value so as to make it distinguishable from the stored test data value. The test circuitry additionally comprises a clock pulse generator configured to generate a delayed clock pulse.Type: ApplicationFiled: October 21, 2013Publication date: April 24, 2014Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., IMECInventors: Sandeep Kumar Goel, Erik Jan Marinissen
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Patent number: 8680874Abstract: A method and system for testing the functionality of a through-silicon-via in an integrated circuit is disclosed. In one aspect, the functionality is tested by measuring its capacitance from one side only. The capacitance of the TSV can be determined by measuring a timing delay introduced in a measurement circuit due to the presence of the TSV. The timing delay is determined by comparing the timing of measurement signal from the measurement circuit with the timing of a reference signal provided by a reference circuit. The comparison is carried out using a digital timing measurement circuit, such as a time-to-digital converter.Type: GrantFiled: July 29, 2011Date of Patent: March 25, 2014Assignee: IMECInventors: Nikolaos Minas, Erik Jan Marinissen
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Publication number: 20140082421Abstract: A method is provided to test a modular integrated circuit (IC) comprising: testing a module-under-test (MUT) within the IC while causing a controlled toggle rate within a first neighbor module of the MUT; wherein the controlled toggle rate within the first neighbor module is selected so that toggling within the first neighbor module has substantially the same effect upon operation of the MUT that operation of the first neighbor module would have during actual normal functional operation of the first neighbor module.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Applicant: Cadence Design Systems, Inc.Inventors: Erik Jan Marinissen, Sergej Deutsch
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Patent number: 8593170Abstract: A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry.Type: GrantFiled: September 27, 2010Date of Patent: November 26, 2013Assignee: IMECInventors: Geert Van der Plas, Erik-Jan Marinissen, Nikolaos Minas, Paul Marchal
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Publication number: 20130002272Abstract: A test circuit and method for testing through-silicon-vias (TSVs) in three-dimensional integrated circuits (ICs) during each phase of manufacturing is disclosed. In one aspect, the method includes testing for faults in each individual TSV, TSV-under-test, shorts between a TSV-under-test, and TSVs in close proximity and for connections between the TSV-under-test and another tier in the ICs. A test circuit has three switchable current paths connected to a power supply via a pull-up resistor and switches: a calibration path, a short path, and a current measurement path. A power supply is connected to the measurement path, and the calibration path and the short path are connected to ground via respective pull-down resistors. For each TSV-under-test, the desired operation mode is selected by the closure of different combinations of switches. The current flowing through the pull-up resistor in each operation mode indicates whether the TSV-under-test has passed or failed the test.Type: ApplicationFiled: June 30, 2011Publication date: January 3, 2013Applicant: IMECInventors: Mustafa Badaroglu, Erik Jan Marinissen, Paul Marchal
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Publication number: 20120025846Abstract: A method and system for testing the functionality of a through-silicon-via in an integrated circuit is disclosed. In one aspect, the functionality is tested by measuring its capacitance from one side only. The capacitance of the TSV can be determined by measuring a timing delay introduced in a measurement circuit due to the presence of the TSV. The timing delay is determined by comparing the timing of measurement signal from the measurement circuit with the timing of a reference signal provided by a reference circuit. The comparison is carried out using a digital timing measurement circuit, such as a time-to-digital converter.Type: ApplicationFiled: July 29, 2011Publication date: February 2, 2012Applicant: IMECInventors: Nikolaos Minas, Erik Jan Marinissen
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Publication number: 20110102011Abstract: A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry.Type: ApplicationFiled: September 27, 2010Publication date: May 5, 2011Applicant: IMECInventors: Geert Van der Plas, Erik-Jan Marinissen, Nikolaos Minas, Paul Marchal
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Publication number: 20100264932Abstract: An integrated circuit (10) comprises a functional circuit (12a-c) that contain information that must be secured against unauthorized access. The integrated circuit comprises a test access circuit (14, 16) coupled to the functional circuit (12a-c), and a plurality of fuse elements (18) coupled to the test access circuit (14, 16). The fuse elements (18) are connected in a circuit configuration that makes the functional circuit (12a-c) consistently accessible via the test access circuit (14, 16) only when first fuse elements (18) of the plurality are in a blown state and second fuse elements (18) of the plurality are in a not-blown state. As a result the integrated circuit can be tested after selectively blowing all of the first fuse elements (18). After testing at least part of the second fuse elements (18) is blown.Type: ApplicationFiled: August 9, 2006Publication date: October 21, 2010Applicant: NXP B.V.Inventors: Erik Jan Marinissen, Sandeepkumar Goel, Andre Krijn Nieuwland, Hubertus Gerardus Hendrikus Vermeulen, Hendrikus Petrus Elisabeth Vranken
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Publication number: 20100223515Abstract: An integrated circuit (10) comprises a scan chain (14) with parallel inputs and outputs coupled to a functional circuit (12a-c). A scan chain modifying circuit (43, 47, 70a-c) is provided coupled to the scan chain (14). When testing is authorized the scan chain modifying circuit operates in a mode wherein a normal shift path is provided through the scan chain. When testing is not authorized the scan chain modifying circuit (43, 47, 70a-c) operates to effect spontaneous dynamic changes in the shift path, which dynamically vary the length of the shift path between external terminals of the integrated circuit while shifting takes place. In an embodiment the dynamical variations are controlled by a running key comparison. In other embodiments running key comparison is used to disable transfer through the scan chain and/or operation of functional circuits.Type: ApplicationFiled: August 9, 2006Publication date: September 2, 2010Applicant: NXP B.V.Inventors: Andre Krijn Nieuwland, Sandeepkumar Goel, Erik Jan Marinissen, Hubertus Gerardus Hendrikus Vermeulen, Hendrikus Petrus Elisabeth Vranken
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Patent number: 7475317Abstract: A method of generating digital test patterns for testing a number of wiring interconnects is described. A first set of test patterns is generated; the number of test patterns in the first set is related to said number of wiring interconnects, and defines a first set of code words. From the first set of code words, a second set of code words is selected. The number of code words in the second set is equal to said number of wiring interconnects, and the selection of the second set of code words is such that the sum of the transition counts for the code words in the second set is minimized.Type: GrantFiled: May 19, 2004Date of Patent: January 6, 2009Assignee: Koninklijke Philips Electronics N.V.Inventors: Erik Jan Marinissen, Hubertus Gerardus Hendrikus Vermeulen, Hendrik Dirk Lodewijk Hollmann
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Patent number: 6829736Abstract: A built-in self-diagnostic (BISD) memory device includes a two-dimension memory array provided with a redundant memory rows and columns that can be substituted for various ones in the two-dimension memory array by an external repair facility. A stimulus generator outputs multi-address test sequences to the memory array during a test mode. A response evaluator receives responses from the memory. A fault table stores evaluations of the responses, and communicates them to the external repair facility. A repair register indicates which memory columns have been intermediately scheduled for repair by the response evaluator. Column counters each accumulate the number of memory bit faults detected in a respective memory column. All are disposed in a single integrated circuit semiconductor device.Type: GrantFiled: May 11, 2001Date of Patent: December 7, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Erik Jan Marinissen, Guillaume Elisabeth Andreas Lousberg, Paul Wielage