Abstract: Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.

Abstract: A method for manufacturing a memory unit capable of storing multibits binary information. A gate is formed on a dielectric layer over a semiconductor substrate. Next, a first etching is performed to etch the semiconductor substrate by using the gate acting as an etching mask to remove exposed surface of the dielectric layer. Subsequently, a first oxide layer is conformally formed on the gate and the semiconductor substrate. An charge-trapping layer is conformally formed on the first oxide layer, and subsequently a second oxide layer is conformally formed on the isolating layer. Next, a second etching is performed to etch the second oxide layer and the charging-trapping layer to form sandwich spacers composed of the second oxide layer/the isolating layer/the first oxide layer on the substrate and the gate sidewall.

Abstract: The present invention includes a semiconductor layer formed over an insulation layer and a substrate. Doped regions are formed in a portion of the semiconductor layer. A gate dielectric and a gate are respectively formed over the semiconductor layer. The arrangement of the gate sidewall and semiconductor layer surface is substantially orthogonal multi-portion dielectric layer is formed on the gate and a portion of the silicon layer. Charge trapping dielectrics are attached on the multi-portion dielectric layer acting as carrier trapping structure. The gate-to-source/drain non-overlapped implantation is capable of storing multi-bits per transistor.

Abstract: A memory system comprising a memory array having a plurality of memory units, a column decoder, a row decoder, a selecting/driving circuit and a sensing circuit is disclosed. Each memory unit comprises a gate electrode coupled to a word lines, a source region coupled to a source line or a first bit line, a drain region coupled to a drain line or a second bit line, a first spacer between the source region and the gate electrode and a second spacer between the drain region and the gate electrode. When a first-bit program operation is performed on the memory unit, a switch-on signal is applied to the gate, a programming signal is applied to the source region and the drain region is switched to ground. As the memory unit is activated, the carriers are injected and stored in a first spacer, thus represents a first bit in the memory unit.

Abstract: The present invention discloses a method for manufacturing memory unit capable of storing multi-bits binary information. Firstly, a gate is formed on a dielectric layer over a semiconductor substrate. Next, a first etching is performed to etch the semiconductor substrate by using the gate acting as an etching mask to remove exposed surface of the dielectric layer. Subsequently, a first oxide layer is conformally formed on the gate and the semiconductor substrate. An charge-trapping layer is conformally formed on the first oxide layer, and subsequently a second oxide layer is conformally formed on the isolating layer. Next, a second etching is performed to etch the second oxide layer and the charging-trapping layer to form sandwich spacers composed of the second oxide layer/the isolating layer/the first oxide layer on the substrate and the gate sidewall.

Abstract: A process for fabricating non-volatile memory by tilt-angle ion implantation comprises essentially the steps of implanting sideling within a nitride dielectric layer heterogeneous elements such as, for example, Ge, Si, N2, O2, and the like, for forming traps capable of capturing more electrons within the nitride dielectric layer such that electrons can be prevented from binding together as the operation time increased; etching off both ends of the original upper and underlying oxide layers to reduce the structural destruction caused by the implantation of heterogeneous elements; and finally, depositing an oxide gate interstitial wall to eradicate electron loss and hence promote the reliability of the device.

Abstract: A memory array including a plurality of word lines, a plurality of first source/drain lines, a plurality of second source/drain lines, and a plurality of memory units. Each memory unit includes a gate electrode coupled to one of the word lines, a first source/drain region coupled to one of the first source/drain lines or first bit lines, a second source/drain region coupled to one of the second source/drain lines or second bit lines, a first spacer between the first source/drain region and the gate electrode to store electrons or electric charges, and a second spacer between the second source/drain region and the gate electrode to store electrons or electric charges.

Abstract: The structure of the nonvolatile memory comprises a substrate having source/drain formed at unselected sides and source/drain with extension source/drain formed at other selected sides. A gate dielectric layer is formed on the substrate and a gate is formed on the gate dielectric layer. An isolation layer is formed along the surface of the gate. Spacers are formed attached on the sidewalls of the gate.

Abstract: The structure of the nonvolatile memory comprises a substrate having source/drain formed at unselected sides and source/drain with extension source/drain formed at other selected sides. A gate dielectric layer is formed on the substrate and a gate is formed on the gate dielectric layer. An isolation layer is formed along the surface of the gate. Spacers are formed attached on the sidewalls of the gate.

Abstract: The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric layer contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate dielectric layer so as to increase the electronic trap density. Then rebuild a new top material after removing the upmost layer of material. Finally, build a gate electrode layer on the gate dielectric layer and form source/drain electrodes at the bases of both sides of the gate dielectric layer. In this invention, with the planting of the hetero element, it will form traps in the gate dielectric layer that can catch electrons more easily. Thus, the electrons won't combine together with the increase of operation time. The storage time can be effectively extended and the problem of the combination of bites can be solved.

Abstract: The present invention discloses a nonvolatile memory with undercut trapping structure, the nonvolatile memory comprising a semiconductor substrate. A gate oxide is formed on the semiconductor substrate. A gate structure is formed on the gate oxide, wherein the gate structure including a undercut structure formed at lower portion of the gate structure and inwardly into the gate structure. An isolation layer is formed over the sidewall of the gate structure. First spacers are formed on the sidewall of the isolation layer and filled into the undercut structure for storing carrier and source and drain regions formed adjacent to the gate structure and under the undercut structure. Salicide is formed on the gate structure and the source and drain regions.

Abstract: The present invention discloses a nonvolatile memory with spacer trapping structure, the nonvolatile memory comprising a semiconductor substrate. A gate oxide is formed on the semiconductor substrate. A gate structure is formed on the gate oxide. An isolation layer is formed over the sidewall of the gate structure. First spacers are formed on the sidewall of the isolation layer and becoming the spacer trapping structure for storing carrier. And the p-n junctions of source and drain regions are formed adjacent to the gate structure. Salicide is formed on the gate structure and the source and drain regions.

Abstract: The present invention discloses a nonvolatile memory with undercut trapping structure, the nonvolatile memory comprising a semiconductor substrate. A gate oxide is formed on the semiconductor substrate. A gate structure is formed on the gate oxide, wherein the gate structure including a undercut structure formed at lower portion of the gate structure and inwardly into the gate structure. An isolation layer is formed over the sidewall of the gate structure. First spacers are formed on the sidewall of the isolation layer and filled into the undercut structure for storing carrier and source and drain regions formed adjacent to the gate structure and under the undercut structure. Salicide is formed on the gate structure and the source and drain regions.