Abstract: The disclosure concerns a method and a control arrangement for controlling valve actuation of an ICE comprising an exhaust valve, an intake valve, and a turbo compressor. The method comprises and the control arrangement is configured to: limiting/limit valve actuation changes of the exhaust and intake valves based on compressor data including surge limit data for the turbo compressor and one or both of a current turbo compressor rotational speed and a current turbo compressor pressure ratio, to maintain a turbo compressor mass flow above a limit mass flow value.

Abstract: A system for charging a battery includes an adapter, and a charger coupled to receive power from the adapter, and to provide a charging current to the battery. The charger includes a power stage with a charge pump to provide the charging current, and a feedback circuit to provide a feedback signal to the adapter. The power stage can be one of: an adjustable current source with voltage clamp, and an adjustable voltage source with current clamp. The charge pump can be implemented as a voltage divider, so that an input adapter current is multiplied by a pre-defined divider ratio to provide the charging current. The charge pump can be one of: single-phase; and multi-phase.

Abstract: The disclosure concerns variable valve timing of a four-stroke ICE. The ICE comprises: an exhaust valve and an intake valve an exhaust camshaft an intake camshaft and a cylinder arrangement. The cylinder arrangement comprises a combustion chamber a cylinder bore and a piston. The control arrangement is configured to: perform a first sequence of changes in the timings of the exhaust and intake camshafts in order to arrive from a first camshaft timing setting at a second camshaft timing setting based on a first current maximum cylinder pressure within the combustion chamber around top dead centre fire and/or around to dead centre gas exchange.

Abstract: In some examples, a converter circuit can be configured to operate in a buck-boost mode. The converter circuit can include a ramp generator that can be configured to generate first and second ramp signals that at least partially overlap respective portions of a buck-boost region during each intermediate clock cycle between clock cycles of a clock signal. By generating the first and second ramp signals during each intermediate clock cycle, first and second drivers can be provided to toggle switches of a power stage, such that an output voltage provided by the power stage can be averaged out over clock cycles of the clock signal to allow for a gradual transition between buck and boost modes of operation of the converter circuit. In some examples, the converter circuit can be configured to operate in a test mode and can be configured to implement trimming of a ramp signal.

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes an amplifier having a first input configured to receive a signal representative of a condition related to a power converter, a second input configured to receive a reference signal, and an output, a PWM regulation circuit having an input coupled to the output of the amplifier, a first output configured to provide a first control signal for a high-side transistor of the power converter, and a second output configured to output a first control signal for a low-side transistor of the power converter, and a PFM regulation circuit having an input coupled to the output of the first amplifier, a first output configured to output a second control signal for the high-side transistor of the power converter, and a second output configured to output a second control signal for the low-side transistor of the power converter.

Abstract: The disclosure concerns variable valve timing of a four-stroke ICE. The ICE comprises: an exhaust valve and an intake valve an exhaust camshaft an intake camshaft and a cylinder arrangement. The cylinder arrangement comprises a combustion chamber a cylinder bore and a piston. The control arrangement is configured to: perform a first sequence of changes in the timings of the exhaust and intake camshafts in order to arrive from a first camshaft timing setting at a second camshaft timing setting based on a first current maximum cylinder pressure within the combustion chamber around top dead centre fire and/or around to dead centre gas exchange.

Abstract: In some examples, a converter circuit can be configured to operate in a buck-boost mode. The converter circuit can include a ramp generator that can be configured to generate first and second ramp signals that at least partially overlap respective portions of a buck-boost region during each intermediate clock cycle between clock cycles of a clock signal. By generating the first and second ramp signals during each intermediate clock cycle, first and second drivers can be provided to toggle switches of a power stage, such that an output voltage provided by the power stage can be averaged out over clock cycles of the clock signal to allow for a gradual transition between buck and boost modes of operation of the converter circuit. In some examples, the converter circuit can be configured to operate in a test mode and can be configured to implement trimming of a ramp signal.

Abstract: This disclosure relates to a multiphase converter design with multi-path phase management circuit and output logic. The phase management circuit and output logic can be employed to implement phase adding and shedding operations based on input and output current information and based on control signals for a power stage of the converter. In some examples, the design employs an estimate of an average output current based on a current at an input of the converter for phase control. In additional examples, the design employs cycle-by-cycle current limit and maximum duty-cycle signals to enable phase quickly during load transient. In further examples, the design employs low input and output-current sensed signals for efficient phase shedding and power saving. The design herein improves an overall accuracy of phase adding and shedding, load transient response performance, an operational efficiency and thermal performance of multiphase converter.

Abstract: One example includes a transconductor system. The system includes a first transconductance amplifier that generates a control current in response to a first input voltage. The system also includes a second transconductance amplifier that generates an output signal in response to a second input voltage. The system further includes an intermediate amplifier that generates a control voltage in response to the control current and a third input voltage. The control voltage can be provided to the first and second transconductance amplifiers to set a transconductance of each of the first and second transconductance amplifiers to be approximately equal.

Abstract: This disclosure relates to a multiphase converter design with multi-path phase management circuit and output logic. The phase management circuit and output logic can be employed to implement phase adding and shedding operations based on input and output current information and based on control signals for a power stage of the converter. In some examples, the design employs an estimate of an average output current based on a current at an input of the converter for phase control. In additional examples, the design employs cycle-by-cycle current limit and maximum duty-cycle signals to enable phase quickly during load transient. In further examples, the design employs low input and output-current sensed signals for efficient phase shedding and power saving. The design herein improves an overall accuracy of phase adding and shedding, load transient response performance, an operational efficiency and thermal performance of multiphase converter.

Abstract: A system for charging a battery includes an adapter, and a charger coupled to receive power from the adapter, and to provide a charging current to the battery. The charger includes a power stage with a charge pump to provide the charging current, and a feedback circuit to provide a feedback signal to the adapter. The power stage can be one of: an adjustable current source with voltage clamp, and an adjustable voltage source with current clamp. The charge pump can be implemented as a voltage divider, so that an input adapter current is multiplied by a pre-defined divider ratio to provide the charging current. The charge pump can be one of: single-phase; and multi-phase.

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes an amplifier having a first input configured to receive a signal representative of a condition related to a power converter, a second input configured to receive a reference signal, and an output, a PWM regulation circuit having an input coupled to the output of the amplifier, a first output configured to provide a first control signal for a high-side transistor of the power converter, and a second output configured to output a first control signal for a low-side transistor of the power converter, and a PFM regulation circuit having an input coupled to the output of the first amplifier, a first output configured to output a second control signal for the high-side transistor of the power converter, and a second output configured to output a second control signal for the low-side transistor of the power converter.

Abstract: One example includes a transconductor system. The system includes a first transconductance amplifier that generates a control current in response to a first input voltage. The system also includes a second transconductance amplifier that generates an output signal in response to a second input voltage. The system further includes an intermediate amplifier that generates a control voltage in response to the control current and a third input voltage. The control voltage can be provided to the first and second transconductance amplifiers to set a transconductance of each of the first and second transconductance amplifiers to be approximately equal.

Abstract: One example includes a transconductor system. The system includes a first transconductance amplifier that generates a control current in response to a first input voltage. The system also includes a second transconductance amplifier that generates an output signal in response to a second input voltage. The system further includes an intermediate amplifier that generates a control voltage in response to the control current and a third input voltage. The control voltage can be provided to the first and second transconductance amplifiers to set a transconductance of each of the first and second transconductance amplifiers to be approximately equal.

Abstract: A system includes a class D amplifier and a current steering digital-to-analog converter (DAC) directly connected to the class D amplifier. The system also includes a common mode servo circuit coupled to a node interconnecting the current steering DAC to the class D amplifier. The common servo circuit amplifies a difference between a common mode signal determined from the node and a reference voltage and generates a feedback current to the node based on the amplified difference. A feed-forward common-mode compensation circuit is included to reduce an alternating current (AC) ripple from the class D amplifier. The feed-forward common-mode compensation circuit includes first and second resistors coupled to respective outputs of the class D amplifier. A current mirror is coupled to the first and second resistors and is configured to sink a current from the node to ground that approximates a common mode feedback current of the class D amplifier.

Abstract: A method for fabrication of vertical nanowire MOSFETs is considered using a gate-last process. The top ohmic electrode is first fabricated and may be used as a mask to form a gate recess using etching techniques. The gate is thereafter formed allowing a large degree in access resistance reduction.

Abstract: One example includes a transconductor system. The system includes a first transconductance amplifier that generates a control current in response to a first input voltage. The system also includes a second transconductance amplifier that generates an output signal in response to a second input voltage. The system further includes an intermediate amplifier that generates a control voltage in response to the control current and a third input voltage. The control voltage can be provided to the first and second transconductance amplifiers to set a transconductance of each of the first and second transconductance amplifiers to be approximately equal.

Abstract: A system for charging a battery includes an adapter, and a charger coupled to receive power from the adapter, and to provide a charging current to the battery. The charger includes a power stage with a charge pump to provide the charging current, and a feedback circuit to provide a feedback signal to the adapter. The power stage can be one of: an adjustable current source with voltage clamp, and an adjustable voltage source with current clamp. The charge pump can be implemented as a voltage divider, so that an input adapter current is multiplied by a pre-defined divider ratio to provide the charging current. The charge pump can be one of: single-phase; and multi-phase.

Abstract: A system includes a class D amplifier and a current steering digital-to-analog converter (DAC) directly connected to the class D amplifier. The system also includes a common mode servo circuit coupled to a node interconnecting the current steering DAC to the class D amplifier. The common servo circuit amplifies a difference between a common mode signal determined from the node and a reference voltage and generates a feedback current to the node based on the amplified difference. A feed-forward common-mode compensation circuit is included to reduce an alternating current (AC) ripple from the class D amplifier. The feed-forward common-mode compensation circuit includes first and second resistors coupled to respective outputs of the class D amplifier. A current mirror is coupled to the first and second resistors and is configured to sink a current from the node to ground that approximates a common mode feedback current of the class D amplifier.

Abstract: One example includes a transconductor system. The system includes a first transconductance amplifier that generates a control current in response to a first input voltage. The system also includes a second transconductance amplifier that generates an output signal in response to a second input voltage. The system further includes an intermediate amplifier that generates a control voltage in response to the control current and a third input voltage. The control voltage can be provided to the first and second transconductance amplifiers to set a transconductance of each of the first and second transconductance amplifiers to be approximately equal.