Abstract: A system and method for automatically updating with hardware clock tree settings on a system-on-a-chip (SOC). A SOC includes a hardware clock control unit (HCCU) coupled to a software interface and a clock tree. The SOC also includes multiple integrated circuit (IC) devices, wherein each IC device receives one or more associated core clocks provided by one or more phase lock loops (PLLs) via the clock tree. The HCCU receives a software-initiated request specifying a given IC device is to be enabled. The HCCU identifies one or more core clocks used by the given IC device. For each one of the identified core clocks, the HCCU configures associated circuitry within the clock tree to generate an identified core clock. The HCCU may also traverse the clock tree and disable clock generating gates found not to drive any other enabled gates or IC devices.

Abstract: Clock-gated synchronizer circuitry includes a number of clock-gated synchronizers, with each clock-gated synchronizer configured to synchronize an asynchronous input signal into a clock domain. The circuitry also includes a clock gater coupled to a clock input of the plurality of clock-gated synchronizers and coupled to receive an input clock and an enable signal. The clock gater is configured to provide the input clock to the plurality of synchronizers only upon receiving the enable signal. The circuitry also includes an enable generator coupled to receive the asynchronous input signals and configured to generate the enable signal for the clock gater responsive to the asynchronous input signals.

Abstract: A multiply accumulate unit (“MAC”) that performs operations on packed integer data. In one embodiment, the MAC receives 2 32-bit data words which, depending on the specified mode of operation, each contain either four 8-bit operands, two 16-bit operands, or one 32-bit operand. Depending on the mode of operation, the MAC performs either sixteen 8×8 operations, four 16×16 operations, or one 32×32 operation. Results may be individually retrieved from registers and the corresponding accumulator cleared after the read cycle. In addition, the accumulators may be globally initialized. Two results from the 8×8 operations may be packed into a single 32-bit register. The MAC may also shift and saturate the products as required.

Abstract: Instructions for performing SIMD instructions, including parallel absolute value and parallel conditional move instructions, as well as a method and circuit for saturating results of operations. The parallel absolute value instruction determines the absolute value of operands based on the sign bit of the operands. When a parallel conditional move instruction is executed, status indicators corresponding to an operand are compared to a condition code in a register to determine whether the condition is true for any of the status indicators; if the condition is true, the corresponding operand is moved to a specified register. A method and circuit for handling saturation of a result of an operation are also provided. When two m-bit operands are added, as in an addition, average, or subtraction operation, if an average instruction is executed, the m most significant bits are output; otherwise, the m least significant bits are output and the result is saturated if there is overflow and saturation is enabled.

Abstract: A multiply accumulate unit (“MAC”) that performs operations on packed integer data. In one embodiment, the MAC receives 2 32-bit data words which, depending on the specified mode of operation, each contain either four 8-bit operands, two 16-bit operands, or one 32-bit operand. Depending on the mode of operation, the MAC performs either sixteen 8×8 operations, four 16×16 operations, or one 32×32 operation. Results may be individually retrieved from registers and the corresponding accumulator cleared after the read cycle. In addition, the accumulators may be globally initialized. Two results from the 8×8 operations may be packed into a single 32-bit register. The MAC may also shift and saturate the products as required.

Abstract: A method and system for DMA transfer of data in scatter/gather mode. A table of buffer descriptors may be used to determine the next buffer to be used when a current buffer storing data that has been transferred or will be transferred and may be used in automatic buffer switching, which does not require processor intervention. Entries in the table of buffer descriptors are entered programmatically. The method and system also provide for hardware writing to table of packet descriptors which describes location and size of incoming data and can indicate whether a packet of data straddles two or more buffers, thus decoupling packet sizes from buffer sizes.