Abstract: A network device can place some or all of the packet processing pipeline into a low-power state for detected idle intervals of sufficient duration. The network device detects idleness greater than a critical duration and automatically engages a low-power mode involving clock throttling and/or clock gating. The power savings in the packet processing pipeline in the network device is based on the average long-term residency in idleness. The idle power is reduced for the packet processing pipeline in the network device by detecting average long-term idleness as a function of the minimum latency of the packet processing pipeline, which is used to reduce the clock rate of the packet processing pipeline, thereby resulting in power savings for the network device.

Abstract: Technologies for processing network packets by a network interface controller (NIC) of a computing device include a network interface, a packet processor, and a controller device of the NIC, each communicatively coupled to a memory fabric of the NIC. The packet processor is configured to receive an event message from the memory fabric and transmit a message to the controller device, wherein the message indicates the network packet has been received and includes the memory fabric location pointer. The controller device is configured to fetch at least a portion of the received network packet from the memory fabric, write an inbound descriptor usable by one or more on-die cores of the NIC to perform an operation on the fetched portion, and restructure the network packet as a function of an outbound descriptor written by the on-die cores subsequent to performing the operation. Other embodiments are described herein.

Abstract: Technologies for processing network packets by a network interface controller (NIC) of a computing device include a network interface, a packet processor, and a controller device of the NIC, each communicatively coupled to a memory fabric of the NIC. The packet processor is configured to receive an event message from the memory fabric and transmit a message to the controller device, wherein the message indicates the network packet has been received and includes the memory fabric location pointer. The controller device is configured to fetch at least a portion of the received network packet from the memory fabric, write an inbound descriptor usable by one or more on-die cores of the NIC to perform an operation on the fetched portion, and restructure the network packet as a function of an outbound descriptor written by the on-die cores subsequent to performing the operation. Other embodiments are described herein.

Abstract: Disclosed is a digitally controlled multi-phase voltage regulator system providing regulated power to electronic components that have variable power requirements. Power is supplied by one or more power integrated circuits (IC) each having a high side power switch controlled by pulse width modulated signals and a low side power switch. The power IC senses voltage at the load and has an on-chip current mirror for generating a current that is a ratio of current delivered to the load. The power IC also has current limiting and on-chip temperature sensing components. The voltage and current information is digitized and provided to a control integrated circuit (IC). The control IC receives this digitized information as well as user provided parameters and, in the regulation mode of operation, provides digitized pulse width modulated control signals to the power IC. In an active transient response mode of operation, the control IC provides signals to turn either the high side switches or low side switches ON.

Abstract: Disclosed is a digitally controlled multi-phase voltage regulator system providing regulated power to electronic components that have variable power requirements. Power is supplied by one or more power integrated circuits (IC) each having a high side power switch controlled by pulse width modulated signals and a low side power switch. The power IC senses voltage at the load and has an on-chip current mirror for generating a current that is a ratio of current delivered to the load. The power IC also has current limiting and on-chip temperature sensing components. The voltage and current information is digitized and provided to a control integrated circuit (IC). The control IC receives this digitized information as well as user provided parameters and, in the regulation mode of operation, provides digitized pulse width modulated control signals to the power IC. In an active transient response mode of operation, the control IC provides signals to turn either the high side switches or low side switches ON.