Patents by Inventor Erik Mentze

Erik Mentze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10199939
    Abstract: A multi-phase switching power converter includes a panic mode detector that triggers the activation of each phase in an open-loop mode of operation in which an open-loop duty cycle is used that is greater than a closed-loop duty cycle used during closed-loop operation for the active phases.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: February 5, 2019
    Assignee: DIALOG SEMICONDUCTOR (UK) LIMITED
    Inventors: Kevin Yi Cheng Chang, James Doyle, Qing Li, Xiaoying Yu, Ibiyemi Omole, Jonathon Stiff, Erik Mentze, Aysel Yildiz
  • Patent number: 10181794
    Abstract: A two-stage multi-phase switching power converter operates its first stage during nominal operation responsive to a nominal clocking frequency and operates its second stage during the nominal operation responsive to a second-stage clocking frequency that is greater than the nominal clocking frequency. In response to an application of a load, the first stage temporarily increases its clocking frequency from the nominal clocking frequency and implements a fixed duty cycle.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: January 15, 2019
    Assignee: DIALOG SEMICONDUCTOR (UK) LIMITED
    Inventors: Kevin Yi Cheng Chang, James Doyle, Erik Mentze
  • Patent number: 10170992
    Abstract: A circuit and a method for power conversion and for generating an output voltage in accordance with a reference voltage are presented. The power converter has a circuit for filtering the output voltage, an error amplifier circuit that compares the reference voltage and the filtered output voltage for generating an error voltage as a result of the comparison. There is a circuit for driving one or more switching devices in dependence on the error voltage. The error amplifier circuit has a first differential circuit and a first bias current generation circuit for generating a first bias current for the first differential circuit, a second differential circuit and a second bias current generation circuit for generating a second bias current for the second differential circuit, and a circuit for redistributing the first bias current to the second differential circuit or redistributing the second bias current to the first differential circuit.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: January 1, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Ibiyemi Omole, James Doyle, Jonathon Stiff, Erik Mentze
  • Publication number: 20050040854
    Abstract: A shifter circuit comprises a high and low voltage buffer stages and an output buffer stage. The high voltage buffer stage comprises multiple transistors arranged in a transistor stack having a plurality of intermediate nodes connecting individual transistors along the stack. The transistor stack is connected between a voltage level being shifted to and an input voltage. An inverter of this stage comprises multiple inputs and an output. Inverter inputs are connected to a respective intermediate node of the transistor stack. The low voltage buffer stage has an input connected to the input voltage and an output, and is operably connected to the high voltage buffer stage. The low voltage buffer stage is connected between a voltage level being shifted away from and a lower voltage. The output buffer stage is driven by the outputs of the high voltage buffer stage inverter and the low voltage buffer stage.
    Type: Application
    Filed: August 18, 2004
    Publication date: February 24, 2005
    Applicant: Idaho Research Foundation, Inc.
    Inventors: Erik Mentze, Herbert Hess, Kevin Buck, David Cox
  • Publication number: 20050040852
    Abstract: Shifter circuits comprise a matched translation stack comprising at least first and second stacks each of which comprising multiple transistors. The matched translation stack is configured to provide a primary logic level shift between a voltage level away from which a shift is desired (VddL) and a voltage level to which the shift is desired (VddH). One or more high voltage buffer stages are provided, at least one of which being connected with and biased by the matched translation stack. At least one high voltage buffer stage comprises multiple transistors arranged in a transistor stack that is biased by the first stack of the matched translation stack, and is connected to receive an input supplied by the second stack of the matched translation stack. The high voltage buffer stage also comprises an inverter that drives an output stage which is also driven by a low voltage buffer stage.
    Type: Application
    Filed: August 18, 2004
    Publication date: February 24, 2005
    Applicant: Idaho Research Foundation, Inc.
    Inventors: Erik Mentze, Herbert Hess, Kevin Buck, David Cox
  • Publication number: 20050040853
    Abstract: A shifter circuit comprises, in one embodiment, an input voltage divider stage comprising multiple transistors arranged in a transistor stack defining a plurality of intermediate nodes. The transistor stack is connected between an input signal and ground and has at least one output. An inverting buffer stage is connected to a supply voltage and coupled to the input voltage divider's output. The inverting buffer stage is configured to provide an inverted output signal. Means are provided for stepping up the inverted output signal, receiving a stepped up output signal and providing a level-shifted output signal at a voltage level lower than that of the input signal.
    Type: Application
    Filed: August 18, 2004
    Publication date: February 24, 2005
    Applicant: Idaho Research Foundation, Inc.
    Inventors: Erik Mentze, Herbert Hess, Kevin Buck, David Cox