Abstract: Described are systems, methods, and computer readable medium for dynamic power usage and data transfer rate management in a sensor network including synchronous and asynchronous links. Exemplary embodiments provide a lightweight communication protocol enabling dynamic management of data buffer size in a sensor network and corresponding control of power usage and data transfer rates in the sensor network.

Abstract: Described are systems, methods, and computer readable medium for dynamic power usage and data transfer rate management in a sensor network including synchronous and asynchronous links. Exemplary embodiments provide a lightweight communication protocol enabling dynamic management of data buffer size in a sensor network and corresponding control of power usage and data transfer rates in the sensor network.

Abstract: A non-volatile memory (12) such as FLASH provides for two modes of operation: command mode and memory mode. Read requests in command mode read non-volatile memory status information, such as from status registers (29). Reads in memory mode return data stored in a non-volatile memory array (20, 22). A command mode read is distinguished from a memory mode read by whether a command mode indication is received within the same memory cycle as a read indication. The command read indication may be an operand address within a prespecified range of memory addresses or through a dedicated input pin. The prespecified memory addresses may be memory-mapped to status registers (29), allowing reads of status registers (29) when an operand address is within the prespecified range without the necessity of entering and leaving command mode, and otherwise to data (20, 22) stored in the non-volatile memory (12).

Abstract: A flash memory (12) has a plurality of banks of memory cells (20, 22). If a read operation of the flash memory (12) is required to the same bank of memory cells in which a program/erase operation is being performed, the program/erase operation is automatically suspended while the read operation is performed. Also, a wait signal is asserted by the flash memory (12) to indicate to a processor (10) that the program/erase operation is being suspended. After the program/erase operation is suspended, the wait signal is negated. If multiple read operations are requested, all the read operations are performed before the program/erase operation resumes.