Patents by Inventor Erik Newton Shreve

Erik Newton Shreve has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11868774
    Abstract: A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: January 9, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Erik Newton Shreve, Eric Thierry Peeters, Per Torstein Roine
  • Publication number: 20210406020
    Abstract: A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.
    Type: Application
    Filed: September 8, 2021
    Publication date: December 30, 2021
    Inventors: Erik Newton Shreve, Eric Thierry Peeters, Per Torstein Roine
  • Patent number: 11138012
    Abstract: A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: October 5, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Erik Newton Shreve, Eric Thierry Peeters, Per Torstein Roine
  • Publication number: 20200293320
    Abstract: A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.
    Type: Application
    Filed: March 31, 2020
    Publication date: September 17, 2020
    Inventors: Erik Newton Shreve, Eric Thierry Peeters, Per Torstein Roine
  • Patent number: 10613864
    Abstract: A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: April 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Erik Newton Shreve, Eric Thierry Peeters, Per Torstein Roine
  • Publication number: 20190286448
    Abstract: A processor with fault generating circuitry responsive to detecting a processor write is to a stack location that is write protected, such as for storing a return address at the stack location.
    Type: Application
    Filed: March 16, 2018
    Publication date: September 19, 2019
    Inventors: Erik Newton Shreve, Eric Thierry Peeters, Per Torstein Roine