Abstract: Disclosed herein is a bridged distributed driver messaging system. This system is especially applicable in IEEE 1394 architectures and AV/C devices, but not limited to such applications. The distributed driver message system includes a means for mapping transports to device IDs without regard to protocols. The bridge aspect disclosed also allows for disparate cabling media to be utilized in a multinode system without regard to protocols, but only with regard to transports.

Abstract: Disclosed herein is a data management system for AV/C descriptor data. The system includes a data container hierarchical structure. The system also includes a methodology for compiling data from the containers into a read buffer upon receipt of a request from a requestor. The data presented to the requestor will preferably be in a format that may be understood by other device requestors that may or may not be utilizing this same container system.

Abstract: Disclosed herein is a data management system for AV/C descriptor data. The system includes a data container hierarchical structure. The system also includes a methodology for compiling data from the containers into a read buffer upon receipt of a request from a requestor. The data presented to the requestor will preferably be in a format that may be understood by other device requestors that may or may not be utilizing this same container system.

Abstract: Disclosed herein is a data management system for AV/C descriptor data. The system includes a data container hierarchical structure. The system also includes a methodology for compiling data from the containers into a read buffer upon receipt of a request from a requestor. The data presented to the requestor will preferably be in a format that may be understood by other device requestors that mayor may not be utilizing this same container system.

Abstract: Disclosed herein is a system for determining communication paths, especially for AV/C devices. The system includes gathering pertinent information about drivers in each available communication between nodes in the system and ordering the driver information in a communication path list string. The system may be employed with multiple nodes having one or more communication paths between nodes. The system may also be employed with multiple nodes where at least one of the nodes is a bridge.

Abstract: Disclosed herein is a data management system for AV/C descriptor data. The system includes a data container hierarchical structure. The system also includes a methodology for compiling data from the containers into a read buffer upon receipt of a request from a requester. The data presented to the requester will preferably be in a format that may be understood by other device requesters that may or may not be utilizing this same container system.

Abstract: Disclosed herein is an automatic ID allocation technique for use in AV/C device applications. The method allows ID assignment without manual user intervention. The method includes assigning an ID to an entity when called to do so upon detection of a new entity. Furthermore, old IDs are reallocated for later use upon disconnection of the associated entity.

Abstract: Disclosed is a system and method for transmitting AV/C data over one or more transports. Further disclosed is a system and method for transmitting AV/C data over non-FCP communication media. The disclosed system and method includes an AV/C transaction delivery system which operates in conjunction with communicatively coupled AV/C protocol layers, AV/C transport layers, and AV/C transport controllers to effectuate transmission of AV/C transaction data without regard to protocol.

Abstract: Disclosed herein is an automatic ID allocation technique for use in AV/C device applications. The method allows ID assignment without manual user intervention. The method includes assigning an ID to an entity when called to do so upon detection of a new entity. Furthermore, old IDs are reallocated for later use upon disconnection of the associated entity.

Abstract: Within a digital network having a bus architecture that complies with the IEEE-1394 Standard for a High Performance Serial Bus a speed map for the digital network is computed by first, computing a first speed between a first node and a second node of the digital network; and second, computing a second speed between the first node and a third node of the digital network using the computed first speed.

Abstract: Disclosed herein is a data management system for AV/C descriptor data. The system includes a data container hierarchical structure. The system also includes a methodology for compiling data from the containers into a read buffer upon receipt of a request from a requester. The data presented to the requestor will preferably be in a format that may be understood by other device requesters that may or may not be utilizing this same container system.

Abstract: Disclosed herein is an automatic ID allocation technique for use in AV/C device applications. The method allows ID assignment without manual user intervention. The method includes assigning an ID to an entity when called to do so upon detection of a new entity. Furthermore, old IDs are reallocated for later use upon disconnection of the associated entity.

Abstract: A cycle master in a digital network having a bus architecture that complies with the IEEE-1394 Standard for a High Performance Serial Bus is calibrated by first computing a clock offset representing a difference between a first time synchronized to each of a plurality of packet arrival events and a second time synchronized to periodic ones of said plurality of packet arrival events; and then adjusting a frame rate of said packet arrival events to compensate for said clock offset.

Abstract: Disclosed herein is a system for determining communication paths, especially for AV/C devices. The system includes gathering pertinent information about drivers in each available communication between nodes in the system and ordering the driver information in a communication path list string. The system may be employed with multiple nodes having one or more communication paths between nodes. The system may also be employed with multiple nodes where at least one of the nodes is a bridge.

Abstract: A cycle master in a digital network having a bus architecture that complies with the IEEE-1394 Standard for a High Performance Serial Bus is calibrated by first computing a clock offset representing a difference between a first time synchronized to each of a plurality of packet arrival events and a second time synchronized to periodic ones of said plurality of packet arrival events; and then adjusting a frame rate of said packet arrival events to compensate for said clock offset.

Abstract: A cycle master in a digital network having a bus architecture that complies with the IEEE-1394 Standard for a High Performance Serial Bus is calibrated by first computing a clock offset representing a difference between a first time synchronized to each of a plurality of packet arrival events and a second time synchronized to periodic ones of said plurality of packet arrival events; and then adjusting a frame rate of said packet arrival events to compensate for said clock offset.

Abstract: Isochronous data packets transmitted within a digital network having a bus architecture that complies with the IEEE-1394 Standard for a High Performance Serial Bus are stamped with a presentation time stamp value determined according to a computed packet rate for the data. For the case where the presentation time stamp field of a first packet of a second frame of data for transmission in the digital network is set with the presentation time value, the packet rate may be computed by measuring a difference between a desired presentation time value of a first packet in a first frame of the data and an actual transmission time of the first packet of the first frame. The first frame preceding the second frame in time of transmission within the network.

Abstract: A computer system comprises a plurality of nodes interconnected by point-to-point links and forms a serial bus. At least one of the plurality of nodes includes an associated configuration memory storing configuration information. The configuration memory is arranged into a plurality of directories according to an hierarchical structure. At least one of directories has a key value which indicates a unique directory entry within the configuration memory, the unique directory entry comprising an extended key value. In one embodiment, the extended key value indicates a driver directory. In a second embodiment, the extended key indicates a protocol directory.

Abstract: A computer system consists of a plurality of nodes, each with an associated local host, coupled together with a plurality of point-to-point links. An isochronous data channel is established within the computer system between a first subset of the plurality of nodes. The isochronous data channel includes a linked list of buffers which are used as temporary storage locations for data transmitted on the isochronous data channel. Each node which is part of the isochronous data channel is configured as a sender or a receiver and data transmissions are commenced. The presence of isochronous data in the channel generates an interrupt which signals a central processing unit (CPU) that data is available. The data is transferred to an associated location within the linked list of buffers and the CPU then moves on to other tasks. In other embodiments, data is transferred using DMA techniques rather than interrupt driven events. Buffers can also be used to transmit isochronous data.

Abstract: A computer system consists of a plurality of nodes, each with an associated local host, coupled together with a plurality of point-to-point links. An isochronous data channel is established within the computer system between a first subset of the plurality of nodes. The isochronous data channel includes a linked list of buffers which are used as temporary storage locations for data transmitted on the isochronous data channel. Each node which is part of the isochronous data channel is configured as a sender or a receiver and data transmissions are commenced. The presence of isochronous data in the channel generates an interrupt which signals a central processing unit (CPU) that data is available. The data is transferred to an associated location within the linked list of buffers and the CPU then moves on to other tasks. In other embodiments, data is transferred using DMA techniques rather than interrupt driven events. Buffers can also be used to transmit isochronous data.