Abstract: Dynamically identifying performance anti-patterns in a software system is based on a set of documented symptoms that are evaluated in real-time. The evaluation is based on the observed system behavior and its comparison against the documented symptoms of different types of performance issues.

Abstract: An improvement to the process for identifying software problems in performance testing is achieved by dynamically adjusting workloads in real-time to stress the functionality of an application suspected of causing a software problem.

Abstract: A method for dynamically and adaptively monitoring a system based on its running behavior adjusts monitoring levels of the monitored application in real-time. A rules-based mechanism dynamically adjusts monitoring levels in real-time, based on the system's performance observed during a workload run, whether in a production or test environment.

Abstract: Dynamically identifying performance anti-patterns in a software system is based on a set of documented symptoms that are evaluated in real-time. The evaluation is based on the observed system behavior and its comparison against the documented symptoms of different types of performance issues.

Abstract: Dynamically identifying performance anti-patterns in a software system is based on a set of documented symptoms that are evaluated in real-time. The evaluation is based on the observed system behavior and its comparison against the documented symptoms of different types of performance issues.

Abstract: Dynamically identifying performance anti-patterns in a software system is based on a set of documented symptoms that are evaluated in real-time. The evaluation is based on the observed system behavior and its comparison against the documented symptoms of different types of performance issues.

Abstract: An improvement to the process for identifying software problems in performance testing is achieved by dynamically adjusting workloads in real-time to stress the functionality of an application suspected of causing a software problem.

Abstract: A method for dynamically and adaptively monitoring a system based on its running behavior adjusts monitoring levels of the monitored application in real-time. A rules-based mechanism dynamically adjusts monitoring levels in real-time, based on the system's performance observed during a workload run, whether in a production or test environment.

Abstract: Execution states of tasks are inferred from collection of information associated with runtime execution of a computer system. Collection of information may include infrequent samples of executing tasks, the samples which may provide inaccurate executing states. One or more tasks may be aggregated by one or more execution states for determining execution time, idle time, or system policy violations, or combinations thereof.

Abstract: A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.

Abstract: Execution states of tasks are inferred from collection of information associated with runtime execution of a computer system. Collection of information may include infrequent samples of executing tasks, the samples which may provide inaccurate executing states. One or more tasks may be aggregated by one or more execution states for determining execution time, idle time, or system policy violations, or combinations thereof.

Abstract: A system to prevent livelock. An outcome of an event is predicted to form an event outcome prediction. The event outcome prediction is compared with a correct value for a datum to be accessed. An instruction is appended with a real event outcome when the outcome of the event is mispredicted to form an appended instruction. A prediction override bit is set on the appended instruction. Then, the appended instruction is executed with the real event outcome.

Abstract: A method for reducing the number of load instructions in the load reorder queue (LRQ) that are searched when a load instruction is executed by a processor, including dispatching the load instructions; inserting the load instructions in the LRQ in program order; clearing a load received data field; executing the load instructions; checking load reorder queue (LRQ) entries; re-executing the load instruction of the matching LRQ entry; continuing execution; getting the load data; setting the load received data field; comparing a load sequence number (LSQN) of each load instruction to a snoop_safe register contents; ANDing all the load received data bits if the LSQN is greater in magnitude to the snoop_safe; setting the snoop_safe register to the LSQN of the load instruction; searching the LRQ entry; and setting a load_peril_snoop register to the LRQ index value where the first load instruction younger to the snoop_safe was found.

Abstract: A method for reducing entries searched in a load reorder queue (LRQ) when snoop instructions are executed by a processor, including checking load reorder queue (LRQ) entries located between a load_peril_snoop register and a lrq_tail register for addresses matching the address of the snoop; and setting a snooped bit in the LRQ entry for any matches found.

Abstract: This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.

Abstract: According to a first aspect of the invention there is provided a method for profiling computer program executions in a computer processing system having a processor and a memory hierarchy. The method includes the step of executing a computer program. Profile counts are stored in a memory array for events associated with the execution of the computer program. The memory array is separate and distinct from the memory hierarchy so as to not perturb normal operations of the memory hierarchy.

Abstract: A method for reducing the number of times in-flight loads must be searched by store instructions in a multi-threaded processor. A load issue for a thread t_old is frozen for a number of cycles. A t13 new load instruction is rejected. A notification is sent to the rest of the processor that the t_new load instruction has been rejected. A load reorder queue (LRQ) of a t_old is snooped for any load which comes from a cache line L accessed by the load instruction and then forces such loads to be re-executed. Ownership of line L is changed to thread t_new.

Abstract: In a dynamically compiling computer system, a system and method for efficiently transferring control from execution of an instruction in a first representation to a second representation of the instruction is disclosed. The system and method include the setting of a tag for entry points of each instruction in a first representation that has been translated to a second representation. The tag is stored in memory in association with each such instruction. When a given instruction in a first representation is to be executed, the tag is examined, and if it indicates that a translated version of the instruction has previously been generated, control is passed to execution of the instruction in the second representation. The second representation can be a different instruction set representation, or an optimized representation in the same instruction set as the original instruction.

Abstract: A system to prevent livelock. An outcome of an event is predicted to form an event outcome prediction. The event outcome prediction is compared with a correct value for a datum to be accessed. An instruction is appended with a real event outcome when the outcome of the event is mispredicted to form an appended instruction. A prediction override bit is set on the appended instruction. Then, the appended instruction is executed with the real event outcome.

Abstract: A method and apparatus for storing non-critical processor information without imposing significant costs on a processor design is disclosed. Transient data are stored in the processor-local cache hierarchy. An additional control bit forms part of cache addresses, where addresses having the control bit set are designated as “transient storage addresses.” Transient storage addresses are not written back to external main memory and, when evicted from the last level of cache, are discarded. Preferably, transient storage addresses are “privileged” in that they are either not accessible to software or only accessible to supervisory or administrator-level software having appropriate permissions. A number of management functions/instructions are provided to allow administrator/supervisor software to manage and/or modify the behavior of transient cache storage.