Patents by Inventor Erik Richter Altman
Erik Richter Altman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240012731Abstract: A computer-implemented method for detecting anomalies in computing systems includes measuring activity metrics associated with accessing resources of the system by several users. Further, condensed diagnostic data is generated by grouping the users into buckets based on bucket and user attributes, and aggregating the activity metrics across all users in each bucket. Bucket contents are recorded during system's use, during which, analytic embedded data is generated for anomaly detection. The generating includes, for each bucket, capturing the activity metrics for an exceptional user in each bucket without aggregation at a next time interval.Type: ApplicationFiled: July 11, 2022Publication date: January 11, 2024Inventors: Benjamin P. Segal, Donald William Schmidt, Erik Richter Altman
-
Publication number: 20220012741Abstract: Application of multi-task learning technique(s) to machine logic (for example, software) used to detect financial transactions that are fraudulent or at least considered likely to be fraudulent. Some embodiments include adjustments and/or additions to conventional multi-task learning techniques in order to make the multi-task learning techniques more suitable for use in fraud detection software. One example of this is compensation for class imbalances that are to be expected as between the likely-fraud and not-likely-fraud classes of data sets (for example, training data sets, runtime data sets).Type: ApplicationFiled: July 8, 2020Publication date: January 13, 2022Inventors: Jeetu Raj, Erik Richter Altman, Shyam Ramji, Ravi Nair
-
Patent number: 8719548Abstract: A method (and structure) of mapping a memory addressing of a multiprocessing system when it is emulated using a virtual memory addressing of another multiprocessing system includes accessing a local lookaside table (LLT) on a target processor with a target virtual memory address. Whether there is a “miss” in the LLT is determined and, with the miss determined in the LLT, a lock for a global page table is obtained.Type: GrantFiled: April 13, 2011Date of Patent: May 6, 2014Assignee: International Business Machines CorporationInventors: Erik Richter Altman, Ravi Nair, John Kevin O'Brien, Kathryn Mary O'Brien, Peter Howland Oden, Daniel Arthur Prener, Sumeda Wasudeo Sathaye
-
Publication number: 20120144166Abstract: A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.Type: ApplicationFiled: February 10, 2012Publication date: June 7, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erik Richter Altman, Michael Karl Gschwind, Jude A. Rivers, Sumedh W. Sathaye, John-David Wellman, Victor V. Zyuban
-
Patent number: 8151092Abstract: A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit.Type: GrantFiled: January 12, 2005Date of Patent: April 3, 2012Assignee: International Business Machines CorporationInventors: Erik Richter Altman, Michael Karl Gschwind, Jude A. Rivers, Sumedh W. Sathaye, John-David Wellman, Victor V. Zyuban
-
Publication number: 20110191095Abstract: A method (and structure) of mapping a memory addressing of a multiprocessing system when it is emulated using a virtual memory addressing of another multiprocessing system includes accessing a local lookaside table (LLT) on a target processor with a target virtual memory address. Whether there is a “miss” in the LLT is determined and, with the miss determined in the LLT, a lock for a global page table is obtained.Type: ApplicationFiled: April 13, 2011Publication date: August 4, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erik Richter Altman, Ravi Nair, John Kevin O'Brien, Kathryn Mary O'Brien, Peter Howland Oden, Daniel Arthur Prener, Sumeda Wasudeo Sathaye
-
Patent number: 7953588Abstract: A method (and system) for emulating a target system's memory addressing using a virtual-to-real memory mapping mechanism of a host multiprocessor system's operating system, includes inputting a target virtual memory address into a simulated page table to obtain a host virtual memory address. The target system is oblivious to the software it is running on.Type: GrantFiled: September 17, 2002Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Erik Richter Altman, Ravi Nair, John Kevin O'Brien, Kathryn Mary O'Brien, Peter Howland Oden, Daniel Arthur Prener, Sumedh Wasudeo Sathaye
-
Patent number: 7844446Abstract: A method (and system) for executing a multiprocessor program written for a target instruction set architecture on a host computing system having a plurality of processors designed to process instructions of a second instruction set architecture, includes representing each portion of the program designed to run on a processor of the target computing system as one or more program threads to be executed on the host computing system.Type: GrantFiled: February 19, 2009Date of Patent: November 30, 2010Assignee: International Business Machines CorporationInventors: Erik Richter Altman, Ravi Nair, John Kevin O'Brien, Kathryn Mary O'Brien, Peter Howland Oden, Daniel Arthur Prener, Sumedh Wasudeo Sathaye
-
Publication number: 20090157377Abstract: A method (and system) for executing a multiprocessor program written for a target instruction set architecture on a host computing system having a plurality of processors designed to process instructions of a second instruction set architecture, includes representing each portion of the program designed to run on a processor of the target computing system as one or more program threads to be executed on the host computing system.Type: ApplicationFiled: February 19, 2009Publication date: June 18, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Erik Richter Altman, Ravi Nair, John Kevin O'Brien, Kathryn Mary O'Brien, Peter Howland Oden, Daniel Arthur Prener, Sumedh Wasudeo Sathaye
-
Patent number: 7509457Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.Type: GrantFiled: February 24, 2005Date of Patent: March 24, 2009Assignee: International Business Machines CorporationInventors: Erik Richter Altman, Peter George Capek, Michael Karl Gschwind, Charles Ray Johns, Harm Peter Hofstee, Martin E. Hopkins, James Allan Kahle, Sumedh W. Sathaye, John-David Wellman, Ravi Nair
-
Patent number: 7496494Abstract: A method (and system) for executing a multiprocessor program written for a target instruction set architecture on a host computing system having a plurality of processors designed to process instructions of a second instruction set architecture, includes representing each portion of the program designed to run on a processor of the target computing system as one or more program threads to be executed on the host computing system.Type: GrantFiled: September 17, 2002Date of Patent: February 24, 2009Assignee: International Business Machines CorporationInventors: Erik Richter Altman, Ravi Nair, John Kevin O'Brien, Kathryn Mary O'Brien, Peter Howland Oden, Daniel Arthur Prener, Sumedh Wasudeo Sathaye
-
Publication number: 20080162877Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.Type: ApplicationFiled: March 15, 2008Publication date: July 3, 2008Inventors: Erik Richter Altman, Peter George Capek, Michael Karl Gschwind, Charles Ray Johns, Harm Peter Hofstee, Martin E. Hopkins, James Allan Kahle, Sumedh W. Sathaye, John-David Wellman, Ravi Nair
-
Publication number: 20040054517Abstract: A method (and system) for executing a multiprocessor program written for a target instruction set architecture on a host computing system having a plurality of processors designed to process instructions of a second instruction set architecture, includes representing each portion of the program designed to run on a processor of the target computing system as one or more program threads to be executed on the host computing system.Type: ApplicationFiled: September 17, 2002Publication date: March 18, 2004Applicant: International Business Machines CorporationInventors: Erik Richter Altman, Ravi Nair, John Kevin O'Brien, Kathryn Mary O'Brien, Peter Howland Oden, Daniel Arthur Prener, Sumedh Wasudeo Sathaye
-
Publication number: 20040054518Abstract: A method (and system) for emulating a target system's memory addressing using a virtual-to-real memory mapping mechanism of a host multiprocessor system's operating system, includes inputting a target virtual memory address into a simulated page table to obtain a host virtual memory address. The target system is oblivious to the software it is running on.Type: ApplicationFiled: September 17, 2002Publication date: March 18, 2004Applicant: International Business Machines CorporationInventors: Erik Richter Altman, Ravi Nair, John Kevin O'Brien, Kathryn Mary O'Brien, Peter Howland Oden, Daniel Arthur Prener, Sumedh Wasudeo Sathaye