Abstract: A semiconductor chip having a P? substrate and an N+ epitaxial layer grown on the P? substrate is shown. A P? circuit layer is grown on top of the N+ epitaxial layer. A first moat having an electrically quiet ground connected to a first N+ epitaxial region is created by isolating the first N+ epitaxial region with a first deep trench. The first moat is surrounded, except for a DC path, by a second moat with a second N+ epitaxial region, created by isolating the second N+ epitaxial region with a second deep trench. The second moat may be arranged as a rectangular spiral around the first moat.

Abstract: Systems and computer program products for layout device matching driven by a schematic editor. Exemplary embodiments include identifying a master device in a circuit layout having at least transistors, the master device having property values including at least one of topology, name and device-type, identifying a cloned device linked to the master device, automatically propagating the property values to the cloned device, making changes to a design layout of the master device, including a change to the properties, and automatically propagating the changes to the design layout and the change to the properties of the master device to the cloned device.

Abstract: Systems and computer program products for layout device matching driven by a schematic editor. Exemplary embodiments include identifying a master device in a circuit layout having at least transistors, the master device having property values including at least one of topology, name and device-type, identifying a cloned device linked to the master device, automatically propagating the property values to the cloned device, making changes to a design layout of the master device, including a change to the properties, and automatically propagating the changes to the design layout and the change to the properties of the master device to the cloned device.

Abstract: A system comprising, a processor operative to, receive a first input designating a first net segment profile on a first level in an integrated circuit for shielding, determine whether the designated first net segment profile is in electrical communication with other net segment profiles, determine whether the net segment profiles are located in a different level than the first net segment profile, define a first shielding profile corresponding to the net segment profiles on the first level, define a second shielding profile corresponding to the net segment profiles on the second level, determine and removing segments of the first shielding profile and the second shielding profile contact features of the integrated circuit, determine and removing segments of the first shielding profile and the second shielding profile are non-continuous, define vias at the intersections of first shielding profile and the second shielding profile, and a processor operative to display the output.

Abstract: A method for designing shielding in integrated circuits, the method comprising, receiving a first input designating a first net segment profile on a first level in an integrated circuit for shielding, determining whether the designated first net segment profile is in electrical communication with other net segment profiles, determining whether the net segment profiles are located in a different level than the first net segment profile, defining a first shielding profile corresponding to the net segment profiles on the first level, defining a second shielding profile corresponding to the net segment profiles on the second level, determining and removing segments of the first shielding profile and the second shielding profile contact features of the integrated circuit, determining and removing segments of the first shielding profile and the second shielding profile are non-continuous, defining vias at the intersections of first shielding profile and the second shielding profile.