Abstract: Clocking scheme to clock a monolithic integrated circuit, having a basic clock rate (c0) generated by a clock source which is coupled to N intermediate clocks (c1 through cN) which are delayed relative to each other, wherein the individual delays (t) are distributed within a period T of the basic lock rate. Each of the N intermediate clocks (c1 through cN) supplies at least one of M data-processing blocks (D1 through DM). To effect a transfer of data between a transmitting data-processing block (D2) and a receiving data-processing block (D1), the delay of the intermediate clock assigned to the intermediate clock (c2) is greater than the delay of the intermediate clock (c1) assigned to the receiving data-processing block.

Abstract: Clocking scheme to clock a monolithic integrated circuit, having a basic clock rate (c0) generated by a clock source which is coupled to N intermediate clocks (c1 through cN) which are delayed relative to each other, wherein the individual delays (t) are distributed within a period T of the basic clock rate. Each of the N intermediate clocks (c1 through cN) supplies at least one of M data-processing blocks (D1 through DM). To effect a transfer of data between a transmitting data-processing block (D2) and a receiving data-processing block (D1), the delay of the intermediate clock assigned to the intermediate clock (c2) is greater than the delay of the intermediate clock (c1) assigned to the receiving data-processing block.