Patents by Inventor Erik Spaan

Erik Spaan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9570437
    Abstract: A semiconductor die is disclosed comprising a lateral semiconductor device on an upper major surface of a substrate, the integrated circuit comprising a silicon layer over the substrate, a recess in the silicon layer, a layer of LOCOS silicon oxide within the recess and having a grown upper surface which is coplanar with the surface of an un-recessed portion of the silicon layer, wherein the silicon layer beneath the recess has a non-uniform lateral doping profile, and is comprised in a drift region of the lateral semiconductor device. A method of making such a die is also disclosed, as is an integrated circuit and a driver circuit.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: February 14, 2017
    Assignee: NXP B.V.
    Inventors: Priscilla Boos, Rob van Dalen, Erik Spaan
  • Publication number: 20150194421
    Abstract: A semiconductor die is disclosed comprising a lateral semiconductor device on an upper major surface of a substrate, the integrated circuit comprising a silicon layer over the substrate, a recess in the silicon layer, a layer of LOCOS silicon oxide within the recess and having a grown upper surface which is coplanar with the surface of an un-recessed portion of the silicon layer, wherein the silicon layer beneath the recess has a non-uniform lateral doping profile, and is comprised in a drift region of the lateral semiconductor device. A method of making such a die is also disclosed, as is an integrated circuit and a driver circuit.
    Type: Application
    Filed: May 16, 2014
    Publication date: July 9, 2015
    Applicant: NXP B.V.
    Inventors: Priscilla Boos, Rob van Dalen, Erik Spaan
  • Publication number: 20140203365
    Abstract: There is disclosed a semiconductor device. The device comprises: a silicon layer; a tapered insulating layer formed on the silicon layer; and a plurality of Bipolar CMOS DMOS device layers formed above the tapered insulating layer. The taper of the tapered insulating layer is in the lower surface of the tapered insulating layer. The tapered insulating layer has a substantially planar upper surface and is at least partially recessed in the silicon layer.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 24, 2014
    Applicant: NXP B.V.
    Inventors: Priscilla Boos, Rob van Dalen, Erik Spaan
  • Patent number: 8487719
    Abstract: A resonator comprises a bottom electrode layer (12), a top electrode layer (10) which defines a resonator body; and a piezoelectric layer (14) sandwiched between the top and bottom electrode layers. An external region (152) is provided around the outside of the periphery of the resonator body. The cutoff frequency of a first resonance mode of the external region (152) is matched to the cutoff frequency of a second, different, resonance mode of the resonator body. The invention provides a deliberate change (typically increase) in the cutoff frequency the resonance modes in the external region, so that one of the modes has a cutoff frequency close to the cutoff frequency of the fundamental mode of the resonator body.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: July 16, 2013
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Andreras B. M. Jansman, Rensinus C. Strijbos, Erik Spaan, Jan-Willem Lobeek
  • Publication number: 20110037539
    Abstract: A resonator comprises a bottom electrode layer (12), a top electrode layer (10) which defines a resonator body; and a piezoelectric layer (14) sandwiched between the top and bottom electrode layers. An external region (152) is provided around the outside of the periphery of the resonator body. The cutoff frequency of a first resonance mode of the external region (152) is matched to the cutoff frequency of a second, different, resonance mode of the resonator body. The invention provides a deliberate change (typically increase) in the cutoff frequency the resonance modes in the external region, so that one of the modes has a cutoff frequency close to the cutoff frequency of the fundamental mode of the resonator body.
    Type: Application
    Filed: April 24, 2009
    Publication date: February 17, 2011
    Applicant: NXP B.V.
    Inventors: Andreras B. M. Jansman, Rensinus C. Strijbos, Erik Spaan, Jan-Willem Lobeek