Patents by Inventor Erik Swanson

Erik Swanson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210132985
    Abstract: A processing system includes a processor core and a scheduler coupled to the processor core. The processing system executes a first active thread and a second active thread in the processor core and detects a swap event for the first active thread or the second active thread. Based on the swap event, using a shadow-latch configured fixed mapping system, to the processing system replaces either the first active thread or the second active thread with a shadow-based thread, the shadow-based thread being stored in a shadow-latch configured register file.
    Type: Application
    Filed: October 30, 2019
    Publication date: May 6, 2021
    Inventors: Michael ESTLICK, Erik SWANSON
  • Publication number: 20210117196
    Abstract: A floating point unit includes a non-pickable scheduler queue (NSQ) that offers a load operation concurrently with a load store unit retrieving load data for an operand that is to be loaded by the load operation. The floating point unit also includes a renamer that renames architectural registers used by the load operation and allocates physical register numbers to the load operation in response to receiving the load operation from the NSQ. The floating point unit further includes a set of pickable scheduler queues that receive the load operation from the renamer and store the load operation prior to execution. A physical register file is implemented in the floating point unit and a free list is used to store physical register numbers of entries in the physical register file that are available for allocation.
    Type: Application
    Filed: October 22, 2019
    Publication date: April 22, 2021
    Inventors: Arun A. NAIR, Michael ESTLICK, Erik SWANSON, Sneha V. DESAI, Donglin JI
  • Publication number: 20210096857
    Abstract: A processor includes a load/store unit and an execution pipeline to execute an instruction that represents a single-instruction-multiple-data (SIMD) operation, and which references a memory block storing operand data for one or more lanes of a plurality of lanes and a mask vector indicating which lanes of a plurality of lanes are enabled and which are disabled for the operation. The execution pipeline executes an instruction in a first execution mode unless a memory fault is generated during execution of the instruction in the first execution mode. In response to the memory fault, the execution pipeline re-executes the instruction in a second execution mode. In the first execution mode, a single load operation is attempted to access the memory block via the load/store unit. In the second execution mode, a separate load operation is performed by the load/store unit for each enabled lane of the plurality of lanes prior to executing the SIMD operation.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Inventors: Kai TROESTER, Scott Thomas BINGHAM, John M. KING, Michael ESTLICK, Erik SWANSON, Robert WEIDNER
  • Publication number: 20210096862
    Abstract: A processor includes a front-end with an instruction set that operates at a first bit width and a floating point unit coupled to receive the instruction set in the processor that operates at the first bit width. The floating point unit operates at a second bit width and, based upon a bit width assessment of the instruction set provided to the floating point unit, the floating point unit employs a shadow-latch configured floating point register file to perform bit width reconfiguration. The shadow-latch configured floating point register file includes a plurality of regular latches and a plurality of shadow latches for storing data that is to be either read from or written to the shadow latches. The bit width reconfiguration enables the floating point unit that operates at the second bit width to operate on the instruction set received at the first bit width.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Inventors: Arun A. NAIR, Todd BAUMGARTNER, Michael ESTLICK, Erik SWANSON
  • Publication number: 20210073056
    Abstract: A processor includes a plurality of execution pipes and a distributed scheduler coupled to the plurality of execution pipes. The distributed scheduler includes a first queue to buffer instruction operations from a front end of an instruction pipeline of the processor and a plurality of second queues, wherein each second queue is to buffer instruction operations allocated from the first queue for a corresponding separate subset of execution pipes of the plurality of execution pipes. The distributed scheduler further includes a queue controller to select an allocation mode from a plurality of allocation modes based on whether at least one indicator of an imbalance at the distributed scheduler is detected, and further to control the distributed scheduler to allocate instruction operations from the first queue among the plurality of second queues in accordance with the selected allocation mode.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 11, 2021
    Inventors: Sneha V. DESAI, Michael ESTLICK, Erik SWANSON, Anilkumar RANGANAGOUDRA
  • Publication number: 20210004068
    Abstract: Electrical design current throttling, including: applying an electrical design current (EDC) threshold for each control processing unit component of a plurality of the central processing unit components responsive to the corresponding priority of each central processing unit component, the priority of a central processing unit component responsive to a central processing unit component's current usage data.
    Type: Application
    Filed: May 12, 2020
    Publication date: January 7, 2021
    Inventors: XIUTING KALEEN CHENG MAN, ERIK SWANSON, LARRY D. HEWITT, ADAM N.C. CLARK
  • Patent number: 10626916
    Abstract: A wing foil bearing may include one or more wing or tab foil layers. A tab foil layer may comprise a thin material with a two-dimensional array of tab shapes. A tab shape may be defined by a boundary of material separated from the thin material and having an integral edge and a free edge. Tab shapes may include one or more free-state bends relative to the thin material, forming a two-dimensional array of cantilever wings or tabs. Tab arrays may be one or more of various types or two-dimensional arrays, and a tab foil layer may include additional tab arrays and tabs. One or more tab foil layers may be engaged with a mounting surface layer and a counter-surface layer to form a wing foil bearing. Tab foil layers may be stacked and or nested, including partial nesting and complete nesting.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: April 21, 2020
    Assignee: XDOT ENGINEERING AND ANALYSIS, PLLC
    Inventors: Erik Swanson, Patrick O'Meara
  • Publication number: 20190203761
    Abstract: A wing foil bearing may include one or more wing or tab foil layers. A tab foil layer may comprise a thin material with a two-dimensional array of tab shapes. A tab shape may be defined by a boundary of material separated from the thin material and having an integral edge and a free edge. Tab shapes may include one or more free-state bends relative to the thin material, forming a two-dimensional array of cantilever wings or tabs. Tab arrays may be one or more of various types or two-dimensional arrays, and a tab foil layer may include additional tab arrays and tabs. One or more tab foil layers may be engaged with a mounting surface layer and a counter-surface layer to form a wing foil bearing. Tab foil layers may be stacked and or nested, including partial nesting and complete nesting.
    Type: Application
    Filed: March 8, 2019
    Publication date: July 4, 2019
    Inventors: Erik SWANSON, Patrick O'MEARA
  • Publication number: 20190190536
    Abstract: A processor employs a set of bits to indicate values of portions of registers of a register file. In response to a specified instruction indicating an expected change of instruction types to be executed, the processor sets one or more of the bits and, for subsequent instructions, interprets corresponding portions of the registers as having a specified value (e.g., zero). By employing the set of bits to set the values of the register portions, rather than setting the individual portions of the registers to the specified value, the processor conserves processor resources (e.g., power) when the processor transitions between executing instructions of different types.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 20, 2019
    Inventors: Erik SWANSON, Sneha V. DESAI, Michael ESTLICK
  • Publication number: 20190179643
    Abstract: A coprocessor such as a floating-point unit includes a pipeline that is partitioned into a first portion and a second portion. A controller is configured to provide control signals to the first portion and the second portion of the pipeline. A first physical distance traversed by control signals propagating from the controller to the first portion of the pipeline is shorter than a second physical distance traversed by control signals propagating from the controller to the second portion of the pipeline. A scheduler is configured to cause a physical register file to provide a first subset of bits of an instruction to the first portion at a first time. The physical register file provides a second subset of the bits of the instruction to the second portion at a second time subsequent to the first time.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 13, 2019
    Inventors: Jay FLEISCHMAN, Michael ESTLICK, Michael Christopher SEDMAK, Erik SWANSON, Sneha V. DESAI
  • Publication number: 20190179396
    Abstract: A pipeline includes a first portion configured to process a first subset of bits of an instruction and a second portion configured to process a second subset of the bits of the instruction. A first clock mesh is configured to provide a first clock signal to the first portion of the pipeline. A second clock mesh is configured to provide a second clock signal to the second portion of the pipeline. The first and second clock meshes selectively provide the first and second clock signals based on characteristics of in-flight instructions that have been dispatched to the pipeline but not yet retired. In some cases, a physical register file is configured to store values of bits representative of instructions. Only the first subset is stored in the physical register file in response to the value of the zero high bit indicating that the second subset is equal to zero.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 13, 2019
    Inventors: Jay FLEISCHMAN, Michael ESTLICK, Michael Christopher SEDMAK, Erik SWANSON, Sneha V. DESAI
  • Publication number: 20190146567
    Abstract: A processor is throttled based on accumulated combined current measurements from a plurality of processor cores. The processor monitors activity current levels at each processor core, either directly or indirectly by monitoring specified events at the processor cores. The processor combines (e.g., averages) the activity current levels over a specified duration to determine a combined activity current value (CCV), and compares the CCV value to a threshold, wherein the threshold is based on the maximum current limit of the processor. In response to the CCV exceeding the threshold, the processor throttles one or more of the processor cores, thereby reducing the activity current level at the throttled processor cores and ensuring that the processor operates within its specified current limits.
    Type: Application
    Filed: November 10, 2017
    Publication date: May 16, 2019
    Inventors: Stephen Victor KOSONOCKY, Larry D. HEWITT, Erik SWANSON
  • Patent number: 10267354
    Abstract: A wing foil bearing may include one or more wing or tab foil layers. A tab foil layer may comprise a thin material with a two-dimensional array of tab shapes. A tab shape may be defined by a boundary of material separated from the thin material and having an integral edge and a free edge. Tab shapes may include one or more free-state bends relative to the thin material, forming a two-dimensional array of cantilever wings or tabs. Tab arrays may be one or more of various types or two-dimensional arrays, and a tab foil layer may include additional tab arrays and tabs. One or more tab foil layers may be engaged with a mounting surface layer and a counter-surface layer to form a wing foil bearing. Tab foil layers may be stacked and or nested, including partial nesting and complete nesting.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: April 23, 2019
    Assignee: XDOT ENGINEERING AND ANALYSIS, PLLC
    Inventors: Erik Swanson, Patrick O'Meara
  • Publication number: 20180245625
    Abstract: A wing foil bearing may include one or more wing or tab foil layers. A tab foil layer may comprise a thin material with a two-dimensional array of tab shapes. A tab shape may be defined by a boundary of material separated from the thin material and having an integral edge and a free edge. Tab shapes may include one or more free-state bends relative to the thin material, forming a two-dimensional array of cantilever wings or tabs. Tab arrays may be one or more of various types or two-dimensional arrays, and a tab foil layer may include additional tab arrays and tabs. One or more tab foil layers may be engaged with a mounting surface layer and a counter-surface layer to form a wing foil bearing. Tab foil layers may be stacked and or nested, including partial nesting and complete nesting.
    Type: Application
    Filed: April 23, 2018
    Publication date: August 30, 2018
    Applicant: XDOT ENGINEERING AND ANALYSIS, PLLC
    Inventors: Erik Swanson, Patrick O'Meara
  • Patent number: 9976594
    Abstract: A wing foil bearing may include one or more wing or tab foil layers. A tab foil layer may comprise a thin material with a two-dimensional array of tab shapes. A tab shape may be defined by a boundary of material separated from the thin material and having an integral edge and a free edge. Tab shapes may include one or more free-state bends relative to the thin material, forming a two-dimensional array of cantilever wings or tabs. Tab arrays may be one or more of various types or two-dimensional arrays, and a tab foil layer may include additional tab arrays and tabs. One or more tab foil layers may be engaged with a mounting surface layer and a counter-surface layer to form a wing foil bearing. Tab foil layers may be stacked and or nested, including partial nesting and complete nesting.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: May 22, 2018
    Assignee: XDOT ENGINEERING AND ANALYSIS, PLLC
    Inventors: Erik Swanson, Patrick O'Meara
  • Patent number: 9910638
    Abstract: Square root operations in a computer processor are disclosed. A first iteration for calculating partial results of a square root operation is performed in a larger number of cycles than remaining iterations. The first iteration requires calculation of a first digit that is larger than the subsequent digits. The first iteration thus requires multiplication of values that are larger than corresponding values for the subsequent other digits. By splitting the first digit into two parts, the required multiplications can be performed in less time than if the first digit were not split. Performing these multiplications in less time reduces the total delay for clock cycles associated with the first digit calculations, which increases the possible clock frequency allowed. A multiply-and-accumulate unit that performs either packed-single operations or double-precision operations may be used, along with a combined division/square root unit for simultaneous execution of division and square root operations.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: March 6, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hanbing Liu, John Kelley, Michael Estlick, Erik Swanson, Jay Fleischman
  • Publication number: 20180060039
    Abstract: Square root operations in a computer processor are disclosed. A first iteration for calculating partial results of a square root operation is performed in a larger number of cycles than remaining iterations. The first iteration requires calculation of a first digit that is larger than the subsequent digits. The first iteration thus requires multiplication of values that are larger than corresponding values for the subsequent other digits. By splitting the first digit into two parts, the required multiplications can be performed in less time than if the first digit were not split. Performing these multiplications in less time reduces the total delay for clock cycles associated with the first digit calculations, which increases the possible clock frequency allowed. A multiply-and-accumulate unit that performs either packed-single operations or double-precision operations may be used, along with a combined division/square root unit for simultaneous execution of division and square root operations.
    Type: Application
    Filed: August 25, 2016
    Publication date: March 1, 2018
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Hanbing Liu, John Kelley, Michael Estlick, Erik Swanson, Jay Fleischman
  • Publication number: 20160208848
    Abstract: A wing foil bearing may include one or more wing or tab foil layers. A tab foil layer may comprise a thin material with a two-dimensional array of tab shapes. A tab shape may be defined by a boundary of material separated from the thin material and having an integral edge and a free edge. Tab shapes may include one or more free-state bends relative to the thin material, forming a two-dimensional array of cantilever wings or tabs. Tab arrays may be one or more of various types or two-dimensional arrays, and a tab foil layer may include additional tab arrays and tabs. One or more tab foil layers may be engaged with a mounting surface layer and a counter-surface layer to form a wing foil bearing. Tab foil layers may be stacked and or nested, including partial nesting and complete nesting.
    Type: Application
    Filed: September 10, 2014
    Publication date: July 21, 2016
    Inventors: Erik Swanson, Patrick O'Meara
  • Publication number: 20160058130
    Abstract: A reel-based mechanism for tightening footwear includes a tension member and a plurality of guide members that are positioned about an opening of the footwear. The plurality of guide members guide or direct the tension member about a path along the footwear. The reel-based mechanism further includes a tightening mechanism that is operationally coupled with the tension member to effect tensioning of the tension member and tightening of the footwear upon operation of the tightening mechanism. The tightening mechanism performs one or more secondary functions that are not related to tightening of the footwear.
    Type: Application
    Filed: August 28, 2015
    Publication date: March 3, 2016
    Inventors: Grant Boney, Sean Cavanagh, Jesse Cotterman, Ilya Minkin, Michael Nickel, Rebecca Peterson, Mark Soderberg, Erik Swanson, Aaron Venturini, Tamara White
  • Publication number: 20160035187
    Abstract: An interactive fantasy wagering gaming system and method wherein a virtual community of registered users participate by establishing leagues or contests and place wagers using fantasy gold coins and fantasy league dollars which wagers are tracked to determine the winner of a specific league or contest.
    Type: Application
    Filed: August 1, 2014
    Publication date: February 4, 2016
    Applicant: LAMPS PLUS, INC.
    Inventors: ERIK SWANSON, Jon Knarreborg