Abstract: Described embodiments recover timing and data information from a signal received via a communication channel. An analog-to-digital converter (ADC) operating at a baud rate of the communication channel generates an actual ADC value corresponding to each bit sample of the received signal. A fast symbol estimation module estimates, based on the actual ADC value, a bit value corresponding to each bit sample. The fast symbol estimation module operates at a digital clock rate. The estimated bit values are provided to a timing recovery module. An ADC reconstruction module, based on a first number of pre-cursor estimated bit values, an estimated cursor bit value, and a second number of post-cursor estimated bit values, generates a reconstructed ADC value corresponding to each bit sample. Based on the reconstructed ADC values, the estimated bit values, and the actual ADC values, a corrected bit value is generated for each bit sample.

Abstract: Described embodiments provide a non-uniformly quantized analog-to-digital converter (ADC) for generating a value for each sample of a received signal. The ADC includes arrays of decision comparators provided the received signal. Each comparator has a threshold voltage set according to a corresponding bit history of a predictive decision feedback equalizer (DFE), and each bit history is associated with a tap of the DFE. Each comparator provides a bit value based on the corresponding bit history. The predictive DFE includes a set of interleave groups, each interleave group having j interleaves. Each interleave determines a bit value of a corresponding sample in a window of samples. Each tap corresponds to a feedback path between adjacent interleave groups. Multiplexing logic of each interleave predictively selects a bit value of an associated tap based on a value of a corresponding select line in a previous interleave, thereby alleviating a unit interval timing constraint.

Abstract: Described embodiments calibrate a sampling phase adjustment of a receiver. An analog-to-digital converter generates samples of a received signal at a sample phase. A phase detector selects a window of n samples. If the window includes a Nyquist pattern, a bang-bang trap is enabled that iteratively, for each transition between a first consecutive bit and a second consecutive bit in the Nyquist pattern, samples the received signal at a zero crossing between the first and second consecutive bits and determines the transition polarity. Based on the transition polarity and the zero crossing sample value, the bang-bang trap determines whether the sample phase is correct. If Nyquist patterns are absent from the window, a margin phase detector determines a target voltage margin value and a voltage of a cursor bit of the window. Based on the target voltage margin and voltage, the margin phase detector determines whether the sample phase is correct.

Abstract: Described embodiments adapt one or more taps of a decision feedback equalizer of a receiver by setting a reference voltage for each of one or more data recovery comparators to a corresponding predetermined initial value. The data recovery comparators generate a bit value for each sample of a received signal. A tap adaptation module of the receiver selects a window of n received bit samples. The tap adaptation module iteratively, for each of the one or more data recovery comparators, tracks (i) a detected number of bits having a logic 0 value, and (ii) a detected number of bits having a logic 1 value. The tap adaptation module adjusts, based on a ratio of the detected number of bits having a logic 0 value to the detected number of bits having a logic 1 value, the reference voltage for the corresponding data recovery comparator by a predetermined step amount.

Abstract: Described embodiments provide method of adapting pulse response taps of a receiver. An analog-to-digital converter (ADC) generates an ADC value for each bit sample of a received signal. An error signature analysis (ESA) module defines a window of bit samples and, for the window, estimates a bit value corresponding to each sample based on the ADC value. The ESA module generates (i) a reconstructed ADC value corresponding to an estimated cursor bit based on a number of pre-cursor estimated bits, the estimated cursor bit, and a number of post-cursor estimated bits, and (ii) an error signature value based on the reconstructed ADC value and the ADC value. Based on the error signature value and a minimum pulse response value, it is determined whether the cursor bit corresponds to residual inter-symbol interference (ISI), and, if so, the error signature value is accumulated and tap values for each pulse response tap are adapted.

Abstract: Described embodiments provide a non-uniformly quantized analog-to-digital converter (ADC) for generating a value for each sample of a received signal. The ADC includes arrays of decision comparators, each comparator provided the received signal. Each comparator has a threshold voltage set according to a corresponding bit history of a predictive decision feedback equalizer (DFE), and each bit history is associated with a tap of the DFE. Each comparator provides a bit value based on the corresponding bit history. The predictive DFE includes a set of interleave groups, each interleave group having j interleaves. Each interleave determines a bit value of a corresponding sample in a window of samples. Each tap corresponds to a feedback path between adjacent interleave groups. Multiplexing logic of each interleave predictively selects a bit value of an associated tap based on a value of a corresponding select line in a previous interleave, thereby alleviating a unit interval timing constraint.

Abstract: Described embodiments provide a method of recovering timing data from a received signal. An analog-to-digital converter (ADC) of a receiver generates an actual ADC value for each bit sample of a received signal. Each bit sample occurs at an associated sample phase of the receiver. A margin phase detector of the receiver recovers timing information from the received signal by determining a target voltage margin value. The margin phase detector selects a window of n received bit samples, where n is a positive integer, and determines a voltage of a cursor bit of the selected window of bit samples. The margin phase detector determines, based on the target voltage margin value and the voltage of the cursor bit, whether the sample phase is correct. If the sample phase is incorrect, the margin phase detector adjusts the sample phase of the receiver by a predetermined amount.

Abstract: Described embodiments recover timing data from a received signal. An analog-to-digital converter (ADC) generates a value for each sample of the signal at a sample phase. A phase detector selects a window of n received bit samples, where n is a positive integer. If the bit window includes any Nyquist patterns, the phase detector enables a bang-bang trap. The bang-bang-trap iteratively, for each bit transition between a first consecutive bit and a second consecutive bit in the Nyquist patterns, samples the received signal at a zero crossing between the first and second consecutive bits and determines the polarity of the bit transition. Based on the polarity of the bit transition and the sample value at the zero crossing, the bang-bang trap determines whether the sample phase of the bit sample for the second consecutive bit is correct. If the sample phase is incorrect, the bang-bang trap adjusts the sample phase.

Abstract: Described embodiments adapt one or more taps of a decision feedback equalizer of a receiver by setting a reference voltage for each of one or more data recovery comparators to a corresponding predetermined initial value. The data recovery comparators generate a bit value for each sample of a received signal. A tap adaptation module of the receiver selects a window of n received bit samples. The tap adaptation module iteratively, for each of the one or more data recovery comparators, tracks (i) a detected number of bits having a logic 0 value, and (ii) a detected number of bits having a logic 1 value. The tap adaptation module adjusts, based on a ratio of the detected number of bits having a logic 0 value to the detected number of bits having a logic 1 value, the reference voltage for the corresponding data recovery comparator by a predetermined step amount.

Abstract: Described embodiments calibrate a sampling phase adjustment of a receiver. An analog-to-digital converter generates samples of a received signal at a sample phase. A phase detector selects a window of n samples. If the window includes a Nyquist pattern, a bang-bang trap is enabled. The bang-bang trap iteratively, for each transition between a first consecutive bit and a second consecutive bit in the Nyquist pattern, samples the received signal at a zero crossing between the first and second consecutive bits and determines the transition polarity. Based on the transition polarity and the zero crossing sample value, the bang-bang trap determines whether the sample phase is correct. If Nyquist patterns are absent from the window, a margin phase detector determines a target voltage margin value and a voltage of a cursor bit of the window. Based on the target voltage margin value and the voltage of the cursor bit, the margin phase detector determines whether the sample phase is correct.

Abstract: Described embodiments provide method of adapting pulse response taps of a receiver. An analog-to-digital converter (ADC) generates an ADC value for each bit sample of a received signal. An error signature analysis (ESA) module defines a window of bit samples and, for the window, estimates a bit value corresponding to each sample based on the ADC value. The ESA module generates (i) a reconstructed ADC value corresponding to an estimated cursor bit based on a number of pre-cursor estimated bits, the estimated cursor bit, and a number of post-cursor estimated bits, and (ii) an error signature value based on the reconstructed ADC value and the ADC value. Based on the error signature value and a minimum pulse response value, it is determined whether the cursor bit corresponds to residual inter-symbol interference (ISI), and, if so, the error signature value is accumulated and tap values for each pulse response tap are adapted.

Abstract: Described embodiments recover timing and data information from a signal received via a communication channel. An analog-to-digital converter (ADC) operating at a baud rate of the communication channel generates an actual ADC value corresponding to each bit sample of the received signal. A fast symbol estimation module estimates, based on the actual ADC value, a bit value corresponding to each bit sample. The fast symbol estimation module operates at a digital clock rate. The estimated bit values are provided to a timing recovery module. An ADC reconstruction module, based on a first number of pre-cursor estimated bit values, an estimated cursor bit value, and a second number of post-cursor estimated bit values, generates a reconstructed ADC value corresponding to each bit sample. Based on the reconstructed ADC values, the estimated bit values, and the actual ADC values, a corrected bit value is generated for each bit sample.

Abstract: An apparatus comprising a multiplexer circuit, a plurality of bit generation circuits, and a control circuit. The multiplexer circuit may be configured to generate an intermediate signal in response to (i) a plurality of input bits and (ii) a control signal. The plurality of bit generation circuits may each be configured to generate one of the plurality of input bits. The control circuit may be configured to generate the control signal.

Abstract: An apparatus comprising a multiplexer circuit, a plurality of bit generation circuits, and a control circuit. The multiplexer circuit may be configured to generate an intermediate signal in response to (i) a plurality of input bits and (ii) a control signal. The plurality of bit generation circuits may each be configured to generate one of the plurality of input bits. The control circuit may be configured to generate the control signal.

Abstract: Methods of testing for shorts (e.g., bridging defects) between interconnect lines in an integrated circuit. For example, in a design implemented in a programmable logic device (PLD), some interconnect lines are used and others are unused. To test for shorts between the used and unused interconnect lines, both used and unused interconnect lines are driven to a first logic level, and the leakage current is measured. The used interconnect lines are driven to a second logic level, while the unused lines remain at the first logic level. The current is again measured, and the difference between the two measurements is determined. If the difference exceeds a predetermined threshold, the device design combination is rejected. Some embodiments provide methods of testing for shorts between used and unused interconnect lines for a design targeted to a partially defective PLD.