Abstract: Disclosed herein is a cost effective, efficient, massively parallel multi-wafer test cell. Additionally, this test cell can be used for both single-touchdown and multiple-touchdown applications. The invention uses a novel “split-cartridge” design, combined with a method for aligning wafers when they are separated from the probe card assembly, to create a cost effective, efficient multi-wafer test cell. A “probe-card stops” design may be used within the cartridge to simplify the overall cartridge design and operation.

Abstract: Systems and methods are provided for testing partially completed three-dimensional ICs. Example methods may incorporate one or more of the following features: design for testing (DFT); design for partial wafer test; design for partial probing; partial IC probecards; partial IC test equipment; partial IC quality determinations; partial IC test optimization; and partial test optimization. Other aspects may also be included. Systems and methods incorporating these features to test partially completed three-dimensional ICs may result in saved time and effort, and less scraped material, as the partial device is not built any further when a bad partial device is detected. This results in lower costs and higher yield.

Abstract: A system for use in automated test equipment. In one embodiment, the system includes a configurable integrated circuit (IC) programmable to provide test patterns for use in automated test equipment. The configurable IC includes a configurable interface core that is programmable to provide functionality of one or more protocol based interfaces for a device under test (DUT) and is programmable to interface with the DUT. The system also includes a connection configurable to couple the configurable IC to the DUT.

Abstract: A testing device may include a memory controller managing a transfer of data; and a plurality of interface boards. Each interface board includes a controller buffer. Each controller buffer transfers data between the memory controller and at least one memory module. The memory controller tests the at least one memory module. The testing device is operable to test the at least one memory module independent of an operating rate of the at least one memory module. The memory controller receives operating data of the at least one memory module.

Abstract: An adaptive test system includes one or more reconfigurable test boards, with each test board including at least one re-configurable test processor. The re-configurable test processors can transmit communicate with one another using an inter-processor communications controller associated with each re-configurable test processor. The communications include configuration information, control information, communication protocols, stimulus data, and responses. Configuration information and stimulus data can also be read from a memory. Configuration information is used to configure one or more re-configurable test processors. Once configured, the re-configurable test processor or processors process the data in order to generate one or more test signals. The one or more test signals are then used to test a DUT.

Abstract: A system and method electronically tests devices. The method comprises receiving a first testing model including a first plurality of parameters and acceptable limits for the first plurality of parameters; receiving a second testing model including a second plurality of parameters and acceptable limits for the second plurality of parameters; receiving a first value for a first parameter from the first plurality of parameters, the first parameter at least partially affecting a second parameter from the second plurality of parameters; determining a second value for the second parameter based on the first value; determining if the first value is within the acceptable limits for the first parameter; determining if the second value is within the acceptable limits for the second parameter; and providing an indication when at least one of the first and second values is outside the acceptable limits for a corresponding one of the first and second parameters.

Abstract: In accordance with one embodiment of the invention, a method of singulated die testing can be implemented. This can be implemented by obtaining a wafer and singulating the dies into individual die pieces. The singulated dies can be arranged in a separated testing arrangement and can even combine dies from multiple wafers as part of the combined arrangement. Then, testing can be implemented on the combined test arrangement.

Abstract: A testing device may include a memory controller managing a transfer of data; and a plurality of interface boards. Each interface board includes a controller buffer. Each controller buffer transfers data between the memory controller and at least one memory module. The memory controller tests the at least one memory module. The testing device is operable to test the at least one memory module independent of an operating rate of the at least one memory module. The memory controller receives operating data of the at least one memory module.

Abstract: A wafer test head and ATE for testing semiconductor wafers. The wafer test head having a plurality of sides that can each be used to test a different semiconductor wafer. The architecture of the wafer test head enables electrical connections to probe card located on two different sides of the wafer test head. Multiple silicon wafers can be tested for proper functionality at the same time or in an interleaved fashion via a single multi-sided wafer test head. The internal architecture of an exemplary wafer test head allows printed circuit cards to be able to electrically connected to multiple wafer test locations on a single wafer test head.

Abstract: A wafer test head and ATE for testing semiconductor wafers. The wafer test head having a plurality of sides that can each be used to test a different semiconductor wafer. The architecture of the wafer test head enables electrical connections to probe card located on two different sides of the wafer test head. Multiple silicon wafers can be tested for proper functionality at the same time or in an interleaved fashion via a single multi-sided wafer test head. The internal architecture of an exemplary wafer test head allows printed circuit cards to be able to electrically connected to multiple wafer test locations on a single wafer test head.

Abstract: An adaptive test system includes one or more reconfigurable test boards, with each test board including at least one re-configurable test processor. The re-configurable test processors can transmit communicate with one another using an inter-processor communications controller associated with each re-configurable test processor. The communications include configuration information, control information, communication protocols, stimulus data, and responses. Configuration information and stimulus data can also be read from a memory. Configuration information is used to configure one or more re-configurable test processors. Once configured, the re-configurable test processor or processors process the data in order to generate one or more test signals. The one or more test signals are then used to test a DUT.

Abstract: A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction.

Abstract: A self-repair system provides resource failure tolerance using an interconnection network that provides interconnection information identifying connections between system resources, redundant resources and ports that are connectable to consumers of the system resources. A controller identifies both defective system resources and the affected sinks connected to the defective system resources from the interconnection network. The controller further identifies compatible resources from the system resources and redundant resources that are capable of replacing the defective system resources for each of the affected sinks from the interconnection network. The controller determines a respective cost associated with each of the compatible resources, and in response to the determined costs, selects at least one of the compatible resources as a replacement resource for each of the defective system resources.

Abstract: Systems and methods of allocating device testing resources are described. In one aspect, a system for allocating m resources for testing devices to n sites of a probe card configured to electrically connect to respective test site locations on a substrate, where m and n are integers and m<n, is described. The system includes a configurable interconnection network that includes a plurality of connections between resources and the probe card sites. The connections enable each test site location to be connected to at least one of the resources over a minimum number of touchdowns of the probe card onto the test sites. Each of the resources is connectable to at most a number of the probe card sites equal to the minimum number of touchdowns. A method of allocating m resources for testing devices to n sites of a probe card configured to electrically connect to respective test site locations on a substrate, where m and n are integers and m<n, also is described.

Abstract: Representative embodiments are generally directed to storing compressed test pattern data on an automated test equipment (ATE) device. In one embodiment, the test pattern data is compressed according to a linear feedback shift register (LFSR). The LFSR may possess a low probability of occurrence of linear dependencies associated with compression of stimulus patterns to enable relatively highly compacted patterns to be compressed. Additionally or alternatively, repeat-filled test pattern data is run length encoded using variable length code words to facilitate parallel decompression within the ATE device.