Patents by Inventor Erik W. Jensen

Erik W. Jensen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of fabricating a via attached to a bond pad utilizing a tapered interconnect
    Patent number: 7638419
    Abstract: Various embodiments include a method of forming an interconnect comprising forming at least two vias in a substrate, forming a conductive pad on a surface of the substrate, forming at least one tapered conductive segment on the surface of the substrate coupled to the conductive pad, wherein only a first via of the at least two vias is formed substantially beneath the conductive pad and is coupled to the conductive pad, a second via of the at least two vias is coupled to the conductive pad by a first one of the at least one tapered conductive segments, the first one of the tapered conductive segments having a first end having a first width and a second end having a second width, the first end being connected to the second via and the second end being connected to the conductive pad, the first width being less than the second width.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: December 29, 2009
    Assignee: Intel Corporation
    Inventor: Erik W. Jensen
  • Via attached to a bond pad utilizing a tapered interconnect
    Patent number: 7375432
    Abstract: An interconnect includes a pad and at least two vias coupled to the pad. In one embodiment, the pad has five substantially straight edges, one via directly coupled to the pad by being formed substantially beneath the pad, and one via coupled to one of the five substantially straight edges by a tapered conductive segment. In another embodiment, the pad has three vias directly coupled to the pad and formed substantially beneath the pad. A method of forming an interconnect includes forming at least two vias in a substrate and coupling a pad to each of the at least two vias.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: May 20, 2008
    Assignee: Intel Corporation
    Inventor: Erik W. Jensen
  • Interconnect
    Patent number: 7088002
    Abstract: An interconnect includes a pad and at least two vias coupled to the pad. In one embodiment, the pad has five substantially straight edges, one via directly coupled to the pad by being formed substantially beneath the pad, and one via coupled to one of the five substantially straight edges by a tapered conductive segment. In another embodiment, the pad has three vias directly coupled to the pad and formed substantially beneath the pad. A method of forming an interconnect includes forming at least two vias in a substrate and coupling a pad to each of the at least two vias.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: August 8, 2006
    Assignee: Intel Corporation
    Inventor: Erik W. Jensen
  • Interconnect
    Publication number: 20020074161
    Abstract: An interconnect includes a pad and at least two vias coupled to the pad. In one embodiment, the pad has five substantially straight edges, one via directly coupled to the pad by being formed substantially beneath the pad, and one via coupled to one of the five substantially straight edges by a tapered conductive segment. In another embodiment, the pad has three vias directly coupled to the pad and formed substantially beneath the pad. A method of forming an interconnect includes forming at least two vias in a substrate and coupling a pad to each of the at least two vias.
    Type: Application
    Filed: December 18, 2000
    Publication date: June 20, 2002
    Applicant: Intel Corporation
    Inventor: Erik W. Jensen