Patents by Inventor Erika Kato

Erika Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200123553
    Abstract: The present invention relates to a method for introducing a substance into a plant.
    Type: Application
    Filed: March 28, 2017
    Publication date: April 23, 2020
    Applicants: JAPAN TOBACCO INC., TOKYO METROPOLITAN UNIVERSITY, RIKEN
    Inventors: Norio KATO, Takashi OKAMOTO, Takatoshi KIBA, Erika TODA
  • Publication number: 20190390207
    Abstract: The present invention relates to a method for introducing a substance into a plant. The method of the present invention comprises introducing a substance into a plant germ cell with incomplete cell wall formation.
    Type: Application
    Filed: January 31, 2018
    Publication date: December 26, 2019
    Applicants: JAPAN TOBACCO INC., RIKEN, TOKYO METROPOLITAN UNIVERSITY
    Inventors: Norio KATO, Masako ICHIKAWA, Takashi OKAMOTO, Narumi KOISO, Takatoshi KIBA, Erika TODA
  • Patent number: 9450139
    Abstract: A method for forming an amorphous semiconductor which contains an impurity element and has low resistivity and a method for manufacturing a semiconductor device with excellent electrical characteristics with high yield are provided. In the method for forming an amorphous semiconductor containing an impurity element, which utilizes a plasma CVD method, pulse-modulated discharge inception voltage is applied to electrodes under the pressure and electrode distance with which the minimum discharge inception voltage according to Paschen's Law can be obtained, whereby the amorphous semiconductor which contains an impurity element and has low resistivity is formed.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: September 20, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Erika Kato
  • Patent number: 9443989
    Abstract: A method for forming an amorphous semiconductor which contains an impurity element and has low resistivity and a method for manufacturing a semiconductor device with excellent electrical characteristics with high yield are provided. In the method for forming an amorphous semiconductor containing an impurity element, which utilizes a plasma CVD method, pulse-modulated discharge inception voltage is applied to electrodes under the pressure and electrode distance with which the minimum discharge inception voltage according to Paschen's Law can be obtained, whereby the amorphous semiconductor which contains an impurity element and has low resistivity is formed.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: September 13, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Erika Kato
  • Publication number: 20160111590
    Abstract: A method for forming an amorphous semiconductor which contains an impurity element and has low resistivity and a method for manufacturing a semiconductor device with excellent electrical characteristics with high yield are provided. In the method for forming an amorphous semiconductor containing an impurity element, which utilizes a plasma CVD method, pulse-modulated discharge inception voltage is applied to electrodes under the pressure and electrode distance with which the minimum discharge inception voltage according to Paschen's Law can be obtained, whereby the amorphous semiconductor which contains an impurity element and has low resistivity is formed.
    Type: Application
    Filed: December 22, 2015
    Publication date: April 21, 2016
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro TANAKA, Erika KATO
  • Patent number: 9240493
    Abstract: A method for forming an amorphous semiconductor which contains an impurity element and has low resistivity and a method for manufacturing a semiconductor device with excellent electrical characteristics with high yield are provided. In the method for forming an amorphous semiconductor containing an impurity element, which utilizes a plasma CVD method, pulse-modulated discharge inception voltage is applied to electrodes under the pressure and electrode distance with which the minimum discharge inception voltage according to Paschen's Law can be obtained, whereby the amorphous semiconductor which contains an impurity element and has low resistivity is formed.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: January 19, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Erika Kato
  • Patent number: 9048327
    Abstract: An embodiment of the present invention is a microcrystalline semiconductor film having a thickness of more than or equal to 70 nm and less than or equal to 100 nm and including a crystal grain partly projecting from a surface of the microcrystalline semiconductor film. The crystal grain has an orientation plane and includes a crystallite having a size of 13 nm or more. Further, the film density of the microcrystalline semiconductor film is higher than or equal to 2.25 g/cm3 and lower than or equal to 2.35 g/cm3, preferably higher than or equal to 2.30 g/cm3 and lower than or equal to 2.33 g/cm3.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: June 2, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Takashi Ienaga, Ryu Komatsu, Erika Kato, Ryota Tajima, Yasuhiro Jinbo
  • Patent number: 9018109
    Abstract: A thin film transistor in which deterioration at initial operation is not likely to be caused and a manufacturing method thereof. A transistor which includes a gate insulating layer at least whose uppermost surface is a silicon nitride layer, a semiconductor layer over the gate insulating layer, and a buffer layer over the semiconductor layer and in which the concentration of nitrogen in the vicinity of an interface between the semiconductor layer and the gate insulating layer, which is in the semiconductor layer is lower than that of the buffer layer and other parts of the semiconductor layer. Such a thin film transistor can be manufactured by exposing the gate insulating layer to an air atmosphere and performing plasma treatment on the gate insulating layer before the semiconductor layer is formed.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: April 28, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Erika Kato, Kunihiko Suzuki
  • Patent number: 8956934
    Abstract: An object is to provide a thin film transistor with small off current, large on current, and high field-effect mobility. A silicon nitride layer and a silicon oxide layer which is formed by oxidizing the silicon nitride layer are stacked as a gate insulating layer, and crystals grow from an interface of the silicon oxide layer of the gate insulating layer to form a microcrystalline semiconductor layer; thus, an inverted staggered thin film transistor is manufactured. Since crystals grow from the gate insulating layer, the thin film transistor can have a high crystallinity, large on current, and high field-effect mobility. In addition, a buffer layer is provided to reduce off current.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Miyako Nakajima, Hidekazu Miyairi, Toshiyuki Isa, Erika Kato, Mitsuhiro Ichijo, Kazutaka Kuriki, Tomokazu Yokoi
  • Patent number: 8916425
    Abstract: A seed crystal including mixed phase grains having high crystallinity with a low grain density is formed under a first condition, and a microcrystalline semiconductor film is formed over the seed crystal under a second condition which allows the mixed phase grains in the seed crystal to grow to fill a space between the mixed phase grains. In the first condition, the flow rate of hydrogen is 50 times or greater and 1000 times or less that of a deposition gas containing silicon or germanium, and the pressure in a process chamber is greater than 1333 Pa and 13332 Pa or less. In the second condition, the flow rate of hydrogen is 100 times or greater and 2000 times or less that of a deposition gas containing silicon or germanium, and the pressure in the process chamber is 1333 Pa or greater and 13332 Pa or less.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: December 23, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryota Tajima, Tetsuhiro Tanaka, Takashi Ohtsuki, Ryo Tokumaru, Yuji Egi, Erika Kato, Miyako Morikubo
  • Patent number: 8828859
    Abstract: A microcrystalline semiconductor film is formed over a substrate using a plasma CVD apparatus which includes a reaction chamber in such a manner that a deposition gas and hydrogen are supplied to the reaction chamber in which the substrate is set between a first electrode and a second electrode; and plasma is generated in the reaction chamber by supplying high-frequency power to the first electrode. Note that the plasma density in a region overlapping with an end portion of the substrate in a region where the plasma is generated is set to be higher than that in a region which is positioned more on the inside than the region overlapping with the end portion of the substrate, so that the microcrystalline semiconductor film is formed over a region which is positioned more on the inside than the end portion of the substrate.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Ryo Tokumaru, Takashi Ohtsuki, Ryota Tajima, Erika Kato
  • Patent number: 8344378
    Abstract: An object is to provide a thin film transistor with small off current, large on current, and high field-effect mobility. A silicon nitride layer and a silicon oxide layer which is formed by oxidizing the silicon nitride layer are stacked as a gate insulating layer, and crystals grow from an interface of the silicon oxide layer of the gate insulating layer to form a microcrystalline semiconductor layer; thus, an inverted staggered thin film transistor is manufactured. Since crystals grow from the gate insulating layer, the thin film transistor can have a high crystallinity, large on current, and high field-effect mobility. In addition, a buffer layer is provided to reduce off current.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Miyako Nakajima, Hidekazu Miyairi, Toshiyuki Isa, Erika Kato, Mitsuhiro Ichijo, Kazutaka Kuriki, Tomokazu Yokoi
  • Publication number: 20120208360
    Abstract: A microcrystalline semiconductor film is formed over a substrate using a plasma CVD apparatus which includes a reaction chamber in such a manner that a deposition gas and hydrogen are supplied to the reaction chamber in which the substrate is set between a first electrode and a second electrode; and plasma is generated in the reaction chamber by supplying high-frequency power to the first electrode. Note that the plasma density in a region overlapping with an end portion of the substrate in a region where the plasma is generated is set to be higher than that in a region which is positioned more on the inside than the region overlapping with the end portion of the substrate, so that the microcrystalline semiconductor film is formed over a region which is positioned more on the inside than the end portion of the substrate.
    Type: Application
    Filed: February 8, 2012
    Publication date: August 16, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Tetsuhiro TANAKA, Ryo TOKUMARU, Takashi OHTSUKI, Ryota TAJIMA, Erika KATO
  • Publication number: 20120187408
    Abstract: An embodiment of the present invention is a microcrystalline semiconductor film having a thickness of more than or equal to 70 nm and less than or equal to 100 nm and including a crystal grain partly projecting from a surface of the microcrystalline semiconductor film. The crystal grain has an orientation plane and includes a crystallite having a size of 13 nm or more. Further, the film density of the microcrystalline semiconductor film is higher than or equal to 2.25 g/cm3 and lower than or equal to 2.35 g/cm3, preferably higher than or equal to 2.30 g/cm and lower than or equal to 2.33 g/cm3.
    Type: Application
    Filed: January 20, 2012
    Publication date: July 26, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Tetsuhiro TANAKA, Takashi Ienaga, Ryu Komatsu, Erika Kato, Ryota Tajima, Yasuhiro Jinbo
  • Publication number: 20120021570
    Abstract: A seed crystal including mixed phase grains having high crystallinity with a low grain density is formed under a first condition, and a microcrystalline semiconductor film is formed over the seed crystal under a second condition which allows the mixed phase grains in the seed crystal to grow to fill a space between the mixed phase grains. In the first condition, the flow rate of hydrogen is 50 times or greater and 1000 times or less that of a deposition gas containing silicon or germanium, and the pressure in a process chamber is greater than 1333 Pa and 13332 Pa or less. In the second condition, the flow rate of hydrogen is 100 times or greater and 2000 times or less that of a deposition gas containing silicon or germanium, and the pressure in the process chamber is 1333 Pa or greater and 13332 Pa or less.
    Type: Application
    Filed: July 18, 2011
    Publication date: January 26, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Ryota TAJIMA, Tetsuhiro TANAKA, Takashi OHTSUKI, Ryo TOKUMARU, Yuji EGI, Erika KATO, Miyako MORIKUBO
  • Publication number: 20120003787
    Abstract: A method for forming an amorphous semiconductor which contains an impurity element and has low resistivity and a method for manufacturing a semiconductor device with excellent electrical characteristics with high yield are provided. In the method for forming an amorphous semiconductor containing an impurity element, which utilizes a plasma CVD method, pulse-modulated discharge inception voltage is applied to electrodes under the pressure and electrode distance with which the minimum discharge inception voltage according to Paschen's Law can be obtained, whereby the amorphous semiconductor which contains an impurity element and has low resistivity is formed.
    Type: Application
    Filed: June 29, 2011
    Publication date: January 5, 2012
    Inventors: Tetsuhiro Tanaka, Erika Kato
  • Patent number: 7962549
    Abstract: Methods for creating an interactive gaming environment are provided. In various embodiments, methods of the present invention may include initializing an interactive game application at a game server which is then characterized as having an active status, notifying a lobby server concerning the active status of the game server, registering the application with a universe management server via the lobby server, and allowing users to join the interactive gaming environment. The users joining the interactive gaming environment may be identified by a server key obtained from the game server.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: June 14, 2011
    Assignee: Sony Computer Entertainment America LLC
    Inventors: Shekhar V. Dhupelia, Glen Van Datta, Brian Fernandes, Eiko Erika Kato, William McCarroll
  • Patent number: 7930345
    Abstract: Methods for creating an interactive gaming environment are provided. In various embodiments, methods of the present invention may include initializing an interactive game application at a game server which is then characterized as having an active status, notifying a lobby server concerning the active status of the game server, registering the application with a universe management server via the lobby server, and allowing users to join the interactive gaming environment. The users joining the interactive gaming environment may be identified by a server key obtained from the game server.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: April 19, 2011
    Assignee: Sony Computer Entertainment America LLC
    Inventors: Shekhar V. Dhupelia, Glen Van Datta, Brian Fernandes, Eiko Erika Kato, William McCarroll
  • Patent number: 7877509
    Abstract: Systems for balancing distribution of participants in a gaming environment are provided. In various embodiments, systems of the present invention may include multiple application servers each hosting a common game application, a lobby server for assigning new client devices to one of the application servers, and a universe manager for receiving reports from each of the application servers concerning the status of the game application. The universe manager may further instruct the lobby server to reallocate assignment of subsequent new client devices in order to balance the number of client devices assigned to each application servers.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: January 25, 2011
    Assignee: Sony Computer Entertainment America LLC
    Inventors: Shekhar V. Dhupelia, Glen Van Datta, Brian Fernandes, Eiko Erika Kato, William McCarroll
  • Publication number: 20100327281
    Abstract: An object is to provide a thin film transistor with small off current, large on current, and high field-effect mobility. A silicon nitride layer and a silicon oxide layer which is formed by oxidizing the silicon nitride layer are stacked as a gate insulating layer, and crystals grow from an interface of the silicon oxide layer of the gate insulating layer to form a microcrystalline semiconductor layer; thus, an inverted staggered thin film transistor is manufactured. Since crystals grow from the gate insulating layer, the thin film transistor can have a high crystallinity, large on current, and high field-effect mobility. In addition, a buffer layer is provided to reduce off current.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 30, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Miyako NAKAJIMA, Hidekazu MIYAIRI, Toshiyuki ISA, Erika KATO, Mitsuhiro ICHIJO, Kazutaka KURIKI, Tomokazu YOKOI