Abstract: According to one embodiment, a semiconductor memory device includes a substrate having a first region and a second region arranged in a first direction. The first region includes word line layers and interlayer insulating layers laminated in a second direction, a first semiconductor layer opposed to the word line layers, and an electric charge accumulating film disposed between them. The second region includes a part of the word line layers and the interlayer insulating layers, first insulating layers and a part of the interlayer insulating layers that separate from the word line layers, a contact that has an outer peripheral surface connected to the first insulating layers, and a second insulating layer disposed between the word line layers and the first insulating layers. The first insulating layers have side surfaces connected to the word line layers and side surfaces connected to the second insulating layer.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate having a first region and a second region arranged in a first direction. The first region includes word line layers and interlayer insulating layers laminated in a second direction, a first semiconductor layer opposed to the word line layers, and an electric charge accumulating film disposed between them. The second region includes a part of the word line layers and the interlayer insulating layers, first insulating layers and a part of the interlayer insulating layers that separate from the word line layers, a contact that has an outer peripheral surface connected to the first insulating layers, and a second insulating layer disposed between the word line layers and the first insulating layers. The first insulating layers have side surfaces connected to the word line layers and side surfaces connected to the second insulating layer.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate having a first region and a second region arranged in a first direction. The first region includes word line layers and interlayer insulating layers laminated in a second direction, a first semiconductor layer opposed to the word line layers, and an electric charge accumulating film disposed between them. The second region includes a part of the word line layers and the interlayer insulating layers, first insulating layers and a part of the interlayer insulating layers that separate from the word line layers, a contact that has an outer peripheral surface connected to the first insulating layers, and a second insulating layer disposed between the word line layers and the first insulating layers. The first insulating layers have side surfaces connected to the word line layers and side surfaces connected to the second insulating layer.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate having a first region and a second region arranged in a first direction. The first region includes word line layers and interlayer insulating layers laminated in a second direction, a first semiconductor layer opposed to the word line layers, and an electric charge accumulating film disposed between them. The second region includes a part of the word line layers and the interlayer insulating layers, first insulating layers and a part of the interlayer insulating layers that separate from the word line layers, a contact that has an outer peripheral surface connected to the first insulating layers, and a second insulating layer disposed between the word line layers and the first insulating layers. The first insulating layers have side surfaces connected to the word line layers and side surfaces connected to the second insulating layer.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction are stacked one over the other, and include opposed sides extending in the second direction, a plurality of protrusion portions extending from the first side of the electrodes and spaced from one another in the second direction, and an extraction portion extending from the second side of the electrode. First and second contact plugs extend in a third direction orthogonal to the first and second directions, one of each contacting one of the extraction portions, wherein the extraction portion extending from the uppermost of the electrodes is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the electrodes.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction are stacked one over the other, and include opposed sides extending in the second direction, a plurality of protrusion portions extending from the first side of the electrodes and spaced from one another in the second direction, and an extraction portion extending from the second side of the electrode. First and second contact plugs extend in a third direction orthogonal to the first and second directions, one of each contacting one of the extraction portions, wherein the extraction portion extending from the uppermost of the electrodes is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the electrodes.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction are stacked one over the other, and include opposed sides extending in the second direction, a plurality of protrusion portions extending from the first side of the electrodes and spaced from one another in the second direction, and an extraction portion extending from the second side of the electrode. First and second contact plugs extend in a third direction orthogonal to the first and second directions, one of each contacting one of the extraction portions, wherein the extraction portion extending from the uppermost of the electrodes is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the electrodes.

Abstract: A semiconductor memory device includes a memory cell transistor and a word line connected a gate of the memory cell transistor. A first erase voltage is applied to the memory cell transistor when an erasing operation of a first type is performed on the memory cell transistor, and a second erase voltage, lower than the first erase voltage, is applied to the memory cell transistor when an erasing operation of a second type is performed on the memory cell transistor.