Patents by Inventor Eriko SHIGESAWA

Eriko SHIGESAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit
    Patent number: 11533051
    Abstract: According to one embodiment, a semiconductor integrated circuit includes the following configuration. A first transistor has a source and a gate coupled to first and second voltage nodes respectively. A second transistor has a source and a gate coupled to third and second voltage nodes respectively. A third transistor is coupled between the first and second transistors. A fourth transistor has a source coupled to the first voltage node and a gate coupled to a first output node between the second and third transistors. A fifth transistor has a source coupled to the third voltage node, a gate coupled to the gate of the fourth transistor and a drain coupled to a drain of the fourth transistor. A sixth transistor has a gate supplied with a voltage output from a second output node between the fourth and fifth transistors and a source coupled to the first voltage node.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: December 20, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Eriko Shigesawa, Akio Ogura
  • SEMICONDUCTOR INTEGRATED CIRCUIT
    Publication number: 20220166428
    Abstract: According to one embodiment, a semiconductor integrated circuit includes the following configuration. A first transistor has a source and a gate coupled to first and second voltage nodes respectively. A second transistor has a source and a gate coupled to third and second voltage nodes respectively. A third transistor is coupled between the first and second transistors. A fourth transistor has a source coupled to the first voltage node and a gate coupled to a first output node between the second and third transistors. A fifth transistor has a source coupled to the third voltage node, a gate coupled to the gate of the fourth transistor and a drain coupled to a drain of the fourth transistor. A sixth transistor has a gate supplied with a voltage output from a second output node between the fourth and fifth transistors and a source coupled to the first voltage node.
    Type: Application
    Filed: September 10, 2021
    Publication date: May 26, 2022
    Inventors: Eriko SHIGESAWA, Akio OGURA