Abstract: An integrated circuit component is provided comprising logic capable of being configured to interface with a first companion integrated circuit and to receive information that is communicated from the first companion integrated circuit, which information was communicated to the first companion integrated circuit via a first portion of a system bus.

Abstract: A method of determining whether to issue a pre-fetch transaction in a memory control system comprising generating a pre-fetch threshold dependent on a demand load of a memory controller, calculating a probability measure of pre-fetch accuracy, comparing the threshold with the calculated probability measure, and determining whether to issue a pre-fetch transaction based upon the comparison of the threshold with the calculated probability measure is provided. A pre-fetch apparatus implemented in a memory control system comprising a pre-fetch threshold generator operable to output a pre-fetch threshold in response to a signal indicative of a memory controller demand load, and a comparator circuit operable to compare the pre-fetch threshold and a probability measure of pre-fetch accuracy, wherein the pre-fetch apparatus issues a pre-fetch transaction on the basis of the comparison by the comparator is provided.

Abstract: A method of determining whether to issue a pre-fetch transaction in a memory control system comprising generating a pre-fetch threshold dependent on a demand load of a memory controller, calculating a probability measure of pre-fetch accuracy, comparing the threshold with the calculated probability measure, and determining whether to issue a pre-fetch transaction based upon the comparison of the threshold with the calculated probability measure is provided. A pre-fetch apparatus implemented in a memory control system comprising a pre-fetch threshold generator operable to output a pre-fetch threshold in response to a signal indicative of a memory controller demand load, and a comparator circuit operable to compare the pre-fetch threshold and a probability measure of pre-fetch accuracy, wherein the pre-fetch apparatus issues a pre-fetch transaction on the basis of the comparison by the comparator is provided.

Abstract: In accordance with an embodiment of the present invention, a system for returning data comprises a storage array operable to store data received from at least one data source, a bypass circuit communicatively coupled with the storage array and operable to simultaneously stage data received from the at least one data source and a read data storage controller communicatively coupled with the storage array and the bypass circuit and operable to select a data return path of minimum latency from a plurality of data return paths for returning data selected from one of the storage array and the bypass circuit, based at least in part on at least one tag associated with each of the at least one data source, to a requesting device.