Patents by Inventor Erin C. Jones
Erin C. Jones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7741165Abstract: A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions.Type: GrantFiled: May 12, 2008Date of Patent: June 22, 2010Assignee: International Business Machines CorporationInventors: Kevin Kok Chan, Robert J. Miller, Erin C. Jones, Atul Ajmera
-
Patent number: 7713837Abstract: Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of ˜2500 mJ/m2 have also be achieved herein.Type: GrantFiled: May 28, 2008Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Kathryn Wilder Guarini, Erin C. Jones, Antonio F. Saavedra, Jr., Leathen Shi, Dinkar V. Singh
-
Patent number: 7566631Abstract: Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of ˜2500 mJ/m2 have also be achieved herein.Type: GrantFiled: April 26, 2006Date of Patent: July 28, 2009Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Kathryn Wilder Guarini, Erin C. Jones, Antonio F. Saavedra, Jr., Leathen Shi, Dinkar V. Singh
-
Publication number: 20080248635Abstract: A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions.Type: ApplicationFiled: May 12, 2008Publication date: October 9, 2008Applicant: International Business Machines CorporationInventors: Kevin Kok Chan, Rober J. Miller, Erin C. Jones, Atul Ajmera
-
Publication number: 20080227270Abstract: Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of ˜2500 mJ/m2 have also be achieved herein.Type: ApplicationFiled: May 28, 2008Publication date: September 18, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Kathryn Wilder Guarini, Erin C. Jones, Antonio F. Saavedra, Leathen Shi, Dinkar V. Singh
-
Patent number: 7387924Abstract: A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions.Type: GrantFiled: September 18, 2006Date of Patent: June 17, 2008Assignee: International Business Machines CorporationInventors: Kevin Kok Chan, Robert J. Miller, Erin C. Jones, Atul Ajmera
-
Patent number: 7361556Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.Type: GrantFiled: July 31, 2006Date of Patent: April 22, 2008Assignee: International Business Machines CorporationInventors: James W. Adkisson, Paul D. Agnello, Arne W. Ballantine, Rama Divakaruni, Erin C. Jones, Edward J. Nowak, Jed H. Rankin
-
Patent number: 7265417Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.Type: GrantFiled: June 16, 2004Date of Patent: September 4, 2007Assignee: International Business Machines CorporationInventors: James W. Adkisson, Paul D. Agnello, Arne W. Ballantine, Rama Divakaruni, Erin C. Jones, Edward J. Nowak, Jed H. Rankin
-
Patent number: 7166521Abstract: A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.Type: GrantFiled: October 4, 2004Date of Patent: January 23, 2007Assignee: International Business Machines CorporationInventors: Diane C. Boyd, Hussein I. Hanafi, Erin C. Jones, Dominic J. Schepis, Leathen Shi
-
Patent number: 7163864Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.Type: GrantFiled: October 18, 2000Date of Patent: January 16, 2007Assignee: International Business Machines CorporationInventors: James W. Adkisson, Paul D. Agnello, Arne W. Ballantine, Rama Divakaruni, Erin C. Jones, Edward J. Nowak, Jed H. Rankin
-
Patent number: 7135391Abstract: A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions.Type: GrantFiled: May 21, 2004Date of Patent: November 14, 2006Assignee: International Business Machines CorporationInventors: Kevin Kok Chan, Rober J. Miller, Erin C. Jones, Atul Ajmera
-
Patent number: 7112845Abstract: A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.Type: GrantFiled: June 18, 2002Date of Patent: September 26, 2006Assignee: International Business Machines CorporationInventors: James W. Adkisson, Paul D. Agnello, Arne W. Ballantine, Rama Divakaruni, Erin C. Jones, Jed H. Rankin
-
Patent number: 6835633Abstract: A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.Type: GrantFiled: July 24, 2002Date of Patent: December 28, 2004Assignee: International Business Machines CorporationInventors: Diane C. Boyd, Hussein I. Hanafi, Erin C. Jones, Dominic J. Schepis, Leathen Shi
-
Patent number: 6833569Abstract: The present invention provides a method for fabricating a planar DGFET having a back gate that is aligned to a front gate. The method of the present invention achieves this alignment by creating a carrier-depleted zone in portions of the back gate. The carrier-depleted zone reduces the capacitance between the source/drain regions and the back gate thereby providing a high-performance self-aligned planar double-gate field effect transistor (DGFET). The present invention also provides a planar DGFET having a back gate that is aligned with the front gate. The front to back gate alignment is achieved by providing a carrier-depleted zone in portions of the back gate.Type: GrantFiled: December 23, 2002Date of Patent: December 21, 2004Assignee: International Business Machines CorporationInventors: Omer H. Dokumaci, Bruce B. Doris, Suryanarayan G. Hegde, Meikei Ieong, Erin C. Jones
-
Patent number: 6797553Abstract: A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.Type: GrantFiled: July 24, 2002Date of Patent: September 28, 2004Assignee: International Business Machines CorporationInventors: James W Adkisson, Arne W. Ballantine, Ramachandra Divakaruni, Jeffrey B. Johnson, Erin C. Jones, Hon-Sum P. Wong
-
Patent number: 6762101Abstract: A double-gate field effect transistor (DGFET) is provided using a damascene-like replacement gate processing step to create sidewall source/drain regions, oxide spacers and gate structures inside a previously formed trench. The damascene-like replacement gate processing step allows for the fabrication of a tapered transistor body region having a thicker body under the contacts which reduces access resistance.Type: GrantFiled: April 11, 2003Date of Patent: July 13, 2004Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Erin C. Jones, Paul M. Solomon, Hon-Sum Phillip Wong
-
Publication number: 20040126993Abstract: Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of 2500 mJ/m2 have also be achieved herein.Type: ApplicationFiled: December 30, 2002Publication date: July 1, 2004Inventors: Kevin K. Chan, Kathryn Wilder Guarini, Erin C. Jones, Antonio F. Saavedra, Leathen Shi, Dinkar V. Singh
-
Publication number: 20040121549Abstract: The present invention provides a method for fabricating a planar DGFET having a back gate that is aligned to a front gate. The method of the present invention achieves this alignment by creating a carrier-depleted zone in portions of the back gate. The carrier-depleted zone reduces the capacitance between the source/drain regions and the back gate thereby providing a high-performance self-aligned planar double-gate field effect transistor (DGFET). The present invention also provides a planar DGFET having a back gate that is aligned with the front gate. The front to back gate alignment is achieved by providing a carrier-depleted zone in portions of the back gate.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Inventors: Omer H. Dokumaci, Bruce B. Doris, Suryanarayan G. Hegde, Meikei Ieong, Erin C. Jones
-
Patent number: 6686630Abstract: The present invention provides a method for fabricating sub-0.05 &mgr;m double-gated MOSFET devices utilizing a damascene-gate process. The damascene-gate process provides sub-0.05 &mgr;m double-gated MOSFET devices which include a frontside poly gate electrode and a backside implant region. The two gates are separated by two gate dielectrics that include a thin (on the order of about 200 Å or less) Si layer which is sandwiched between the gate dielectrics. The Si layer serves as the channel region of the device. Short-channel effects are greatly suppressed in the present double-gate MOSFET device because the two gates terminate the drain filed lines, preventing the drain potential from being felt at the source end of the channel.Type: GrantFiled: February 7, 2001Date of Patent: February 3, 2004Assignee: International Business Machines CorporationInventors: Hussein Ibrahim Hanafi, Erin C. Jones, Cheruvu Suryanarayana Murthy, Philip Joseph Oldiges, Leathen Shi
-
Publication number: 20040018699Abstract: A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.Type: ApplicationFiled: July 24, 2002Publication date: January 29, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Diane C. Boyd, Hussein I. Hanafi, Erin C. Jones, Dominic J. Schepis, Leathen Shi