Abstract: Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.

Abstract: Data requests for data stored in a non-volatile media may be monitored and used to identify if the media is being used as memory or storage. The accessibility of the data may be modified based on the identified usage model.

Abstract: Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.

Abstract: Example implementations relate to dynamic random-access memory (DRAM) row sparing. In example implementations, utilization of a failed row of a DRAM device may be excluded. A fuse in the DRAM device may be blown to replace the failed row with a spare row. The fuse may be blown during runtime operation of the DRAM device. Error-correcting code (ECC) may be used to correct erroneous data from the failed row while the fuse is being blown. Accesses of the failed row may be redirected to the spare row after the fuse is blown.

Abstract: Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.

Abstract: Data requests for data stored in a non-volatile media may be monitored and used to identify if the media is being used as memory or storage. The accessibility of the data may be modified based on the identified usage model.

Abstract: Example implementations relate to storing memory erasure information in memory devices on a memory module. In example implementations, a memory location associated with an error in a first cache line may be identified. The first cache line may include data read from the memory location, and the memory location may be in a first memory device of a plurality of memory devices on a memory module. A device number corresponding to the first memory device may be written to one of the plurality of memory devices. When the memory location is read for a second cache line, the device number corresponding to the first memory device may be retrieved. The second cache line may include the retrieved device number and data read from the memory location.

Abstract: Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.

Abstract: Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.

Abstract: Example implementations relate to dynamic random-access memory (DRAM) row sparing. In example implementations, utilization of a failed row of a DRAM device may be excluded. A fuse in the DRAM device may be blown to replace the failed row with a spare row. The fuse may be blown during runtime operation of the DRAM device. Error-correcting code (ECC) may be used to correct erroneous data from the failed row while the fuse is being blown. Accesses of the failed row may be redirected to the spare row after the fuse is blown.

Abstract: Example implementations relate to storing memory erasure information in memory devices on a memory module. In example implementations, a memory location associated with an error in a first cache line may be identified. The first cache line may include data read from the memory location, and the memory location may be in a first memory device of a plurality of memory devices on a memory module. A device number corresponding to the first memory device may be written to one of the plurality of memory devices. When the memory location is read for a second cache line, the device number corresponding to the first memory device may be retrieved. The second cache line may include the retrieved device number and data read from the memory location.

Abstract: Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.

Abstract: A translation look-aside buffer (TLB) is described. The TLB may include a memory populated with pointers to collections (e.g., tables) of virtual-to-physical address translations. The memory may be populated by, for example, a page fault logic in response to resolving a page fault. The TLB may also include a signal logic to receive a virtual address and to selectively provide either a miss signal or a pointer to a collection of virtual-to-physical translations. The signal may provide the miss signal upon determining that the virtual address is not associated with a stored pointer and may provide a pointer upon determining that the virtual address is associated with the pointer.

Abstract: A memory control system is provided with a directory cache and a memory controller. The directory cache has a plurality of directory cache entries configured to store information regarding copies of memory lines stored in a plurality of memory caches, wherein each directory cache entry has one or more bits configured to store an ownership state that indicates whether a corresponding master directory entry lacks a memory cache owner. The memory controller is configured to free for re-use ones of the directory cache entries by 1) accessing a particular directory entry, and 2) determining whether the ownership state of the particular directory cache entry indicates that a corresponding master directory entry lacks a memory cache owner. If so, the memory controller A) skips a master directory update process, and B) claims for re-use the particular directory cache entry.

Abstract: Coherency directory updating is provided in a multiprocessor computing system. A plurality of memory resources have a directory, and are operably connected to an interconnect fabric. A cell is operably connected to the interconnect fabric. The cell has a cache including an entry for each of a plurality of coherency units, each coherency unit included in a memory block representing a contiguous portion of the plurality of memory resources. A controller is operably connected to the interconnect fabric. The controller is configured to control a portion of the plurality of memory resources, and has a comparator configured to identify whether a memory block is local. If the memory block is local, the controller is configured to set a state of the directory to exclusive for a write transaction. If the memory block is not local, the controller is configured to set the state to invalid for a write transaction.

Abstract: A translation look-aside buffer (TLB) is described. The TLB may include a memory populated with pointers to collections (e.g., tables) of virtual-to-physical address translations. The memory may be populated by, for example, a page fault logic in response to resolving a page fault. The TLB may also include a signal logic to receive a virtual address and to selectively provide either a miss signal or a pointer to a collection of virtual-to-physical translations. The signal may provide the miss signal upon determining that the virtual address is not associated with a stored pointer and may provide a pointer upon determining that the virtual address is associated with the pointer.

Abstract: A computer system, related components such as a processor agent, and related method are disclosed. In at least one embodiment, the computer system includes a first core, at least one memory device including a first memory segment, and a first memory controller coupled to the first memory segment. Further, the computer system includes a fabric and at least one processor agent coupled at least indirectly to the first core and the first memory segment, and also coupled to the fabric. A first memory request of the first core in relation to a first memory location within the first memory segment proceeds to the first memory controller by way of the at least one processor agent and the fabric.

Abstract: A directory cache is provided with a plurality of directory entries configured to store information regarding copies of memory lines stored in a plurality of caches. The entries are divided into sets of N entries, with each set of N entries being addressable via an index. The directory cache is also provided with a cache controller. The cache controller retrieves a set of N entries associated with an index corresponding to a memory line, and if a tag portion of one of the retrieved entries corresponds to the memory line, the cache controller determines whether the one of the retrieved entries contains an indication that information regarding the memory line is stored in at least a second one of the retrieved entries.

Abstract: A computer system, related components such as a processor agent, and related method are disclosed. In at least one embodiment, the computer system includes a first core, at least one memory device including a first memory segment, and a first memory controller coupled to the first memory segment. Further, the computer system includes a fabric and at least one processor agent coupled at least indirectly to the first core and the first memory segment, and also coupled to the fabric. A first memory request of the first core in relation to a first memory location within the first memory segment proceeds to the first memory controller by way of the at least one processor agent and the fabric.

Abstract: A memory control system is provided with a directory cache and a memory controller. The directory cache has a plurality of directory cache entries configured to store information regarding copies of memory lines stored in a plurality of memory caches, wherein each directory cache entry has one or more bits configured to store an ownership state that indicates whether a corresponding master directory entry lacks a memory cache owner. The memory controller is configured to free for re-use ones of the directory cache entries by 1) accessing a particular directory entry, and 2) determining whether the ownership state of the particular directory cache entry indicates that a corresponding master directory entry lacks a memory cache owner. If so, the memory controller A) skips a master directory update process, and B) claims for re-use the particular directory cache entry.