Patents by Inventor Ernest A. Goldman

Ernest A. Goldman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4498223
    Abstract: A body of silicon has sectors of N-type and P-type covered by silicon oxide gate layers with adjacent regions covered by a thicker silicon oxide field layer. Gate members of N-type polycrystalline silicon are placed on the gate layers to define an N-type channel region in the N-type sector and a P-type channel region is the P-type sector. P-type conductivity imparting material is introduced into the remaining regions of the N-type sector to convert them to P-type source/drain regions with an intervening N-type channel region, and N-type conductivity imparting material is introduced into the remaining regions of the P-type sector to convert them to N-type source/drain regions with an intervening P-type channel region. The exposed silicon oxide is grown to a thicker field layer and a protective oxide is formed on the polycrystalline gate members.
    Type: Grant
    Filed: April 23, 1982
    Date of Patent: February 12, 1985
    Assignee: GTE Laboratories Incorporated
    Inventors: Ernest A. Goldman, Jeremiah P. McCarthy, Paul E. Poppert
  • Patent number: 4463491
    Abstract: Method of fabricating a monolithic integrated circuit structure incorporating complementary metal-oxide-silicon field effect transistors (CMOS FET's) including providing a body of silicon produced by conventional techniques having a sector of N-type and a sector of P-type each covered by a thin silicon oxide layer and a thin silicon nitride layer. The regions of the body adjacent to each of the sectors are covered by a thicker silicon oxide field layer. Portions of the thin nitride and oxide layers are removed to expose spaced apart zones in each of the sectors. Adherent contact members of low resistivity polycrystalline silicon of N and P-type conductivity are formed in contact with the exposed surfaces of the zone in the P and N-type sectors, respectively. Where N and P-type contact members are contiguous a rectifying junction is produced. The surfaces of the polycrystalline contact members are metallized with a highly conductive material, thereby shorting out the rectifying junctions.
    Type: Grant
    Filed: April 23, 1982
    Date of Patent: August 7, 1984
    Assignee: GTE Laboratories Incorporated
    Inventors: Ernest A. Goldman, Jeremiah P. McCarthy, Paul E. Poppert
  • Patent number: 4151537
    Abstract: Optimized switching and retention characteristics of an MNOS memory device are obtained by using as a gate electrode material either metals or semi-metals having a high work function, in conjunction with a gate dielectric layer having a low density of trapping states throughout its volume. The preferred gate electrode materials are either titanium or p.sup.+ -doped polycrystalline silicon.
    Type: Grant
    Filed: August 5, 1977
    Date of Patent: April 24, 1979
    Assignee: GTE Laboratories Incorporated
    Inventors: Ernest A. Goldman, Moe S. Wasserman