Patents by Inventor Ernest A. Viau, JR.

Ernest A. Viau, JR. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reliability test screen optimization
    Patent number: 9429619
    Abstract: Methods and systems optimize power usage in an integrated circuit design by sorting the integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices to classify the integrated circuit devices into different voltage bins. The methods and systems establish a bin-specific reliability testing processes for each of the voltage bins and test the integrated circuit devices using a tester. This allows the methods and systems to identify as defective ones of the integrated circuit devices that fail the bin-specific integrated circuit reliability testing processes of a corresponding voltage bin. The methods and systems remove the defective ones of the integrated circuit devices to allow only non-defective integrated circuit devices to remain and supply the non-defective integrated circuit devices to a customer.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: August 30, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Theodoros E. Anemikos, Jeanne P. Bickford, Douglas S. Dewey, Ernest A. Viau, Jr.
  • RELIABILITY TEST SCREEN OPTIMIZATION
    Publication number: 20140039664
    Abstract: Methods and systems optimize power usage in an integrated circuit design by sorting the integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices to classify the integrated circuit devices into different voltage bins. The methods and systems establish a bin-specific reliability testing processes for each of the voltage bins and test the integrated circuit devices using a tester. This allows the methods and systems to identify as defective ones of the integrated circuit devices that fail the bin-specific integrated circuit reliability testing processes of a corresponding voltage bin. The methods and systems remove the defective ones of the integrated circuit devices to allow only non-defective integrated circuit devices to remain and supply the non-defective integrated circuit devices to a customer.
    Type: Application
    Filed: August 1, 2012
    Publication date: February 6, 2014
    Applicant: International Business Machines Corporation
    Inventors: THEODOROS E. ANEMIKOS, Jeanne P. Bickford, Douglas S. Dewey, Ernest A. Viau, JR.