Patents by Inventor Ernest Clyde Parker

Ernest Clyde Parker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module
    Patent number: 11172572
    Abstract: A multilayer electronics assembly and associated method of manufacture are provided. The multilayer electronics assembly includes a plurality of stacked substrate layers. Each of the substrate layers is fusion bonded to at least an adjacent one of the plurality of substrate layers. A first discrete electrical circuit component is bonded to a first layer of the plurality of layers. A bonding material is interposed between the discrete electrical circuit component and the first layer. The bonding material has a reflow temperature at which the bonding material becomes flowable that is higher than a fusion bonding temperature of the substrate layers.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: November 9, 2021
    Assignee: Crane Electronics, Inc.
    Inventors: Ernest Clyde Parker, Philip Joseph Lauriello
  • MULTILAYER ELECTRONICS ASSEMBLY AND METHOD FOR EMBEDDING ELECTRICAL CIRCUIT COMPONENTS WITHIN A THREE DIMENSIONAL MODULE
    Publication number: 20180146547
    Abstract: A multilayer electronics assembly and associated method of manufacture are provided. The multilayer electronics assembly includes a plurality of stacked substrate layers. Each of the substrate layers is fusion bonded to at least an adjacent one of the plurality of substrate layers. A first discrete electrical circuit component is bonded to a first layer of the plurality of layers. A bonding material is interposed between the discrete electrical circuit component and the first layer. The bonding material has a reflow temperature at which the bonding material becomes flowable that is higher than a fusion bonding temperature of the substrate layers.
    Type: Application
    Filed: December 28, 2017
    Publication date: May 24, 2018
    Inventors: Ernest Clyde PARKER, Philip Joseph LAURIELLO
  • Multilayer electronics assembly and method for embedding electrical circuit components within a three dimensional module
    Patent number: 9888568
    Abstract: A multilayer electronics assembly and associated method of manufacture are provided. The multilayer electronics assembly includes a plurality of stacked substrate layers. Each of the substrate layers is fusion bonded to at least an adjacent one of the plurality of substrate layers. A first discrete electrical circuit component is bonded to a first layer of the plurality of layers. A bonding material is interposed between the discrete electrical circuit component and the first layer. The bonding material has a reflow temperature at which the bonding material becomes flowable that is higher than a fusion bonding temperature of the substrate layers.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: February 6, 2018
    Assignee: CRANE ELECTRONICS, INC.
    Inventors: Ernest Clyde Parker, Philip Joseph Lauriello
  • Switched capacitor hold-up scheme for constant boost output voltage
    Patent number: 8710820
    Abstract: A power architecture receives an input signal at an input node and converts the input signal into an intermediate signal with a power conversion stage. The power conversion stage supplies the intermediate signal to an output node of the power conversion stage where the intermediate signal is filtered with an operating capacitance coupled to the output node. A hold-up capacitance is charged, and when a loss of the input signal is detected, the hold-up capacitance is coupled to the input node.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: April 29, 2014
    Assignee: Crane Electronics, Inc.
    Inventor: Ernest Clyde Parker
  • SWITCHED CAPACITOR HOLD-UP SCHEME FOR CONSTANT BOOST OUTPUT VOLTAGE
    Publication number: 20110241637
    Abstract: A power architecture receives an input signal at an input node and converts the input signal into an intermediate signal with a power conversion stage. The power conversion stage supplies the intermediate signal to an output node of the power conversion stage where the intermediate signal is filtered with an operating capacitance coupled to the output node. A hold-up capacitance is charged, and when a loss of the input signal is detected, the hold-up capacitance is coupled to the input node.
    Type: Application
    Filed: March 31, 2010
    Publication date: October 6, 2011
    Applicant: INTERPOINT CORPORATION
    Inventor: Ernest Clyde Parker