Abstract: Microelectronic devices having a protected input and methods for manufacturing such microelectronic devices. A microelectronic device has a microelectronic die and a support structure for coupling the die to voltage and signal sources. The microelectronic die can have integrated circuitry and a plurality of bond-pads coupled to the integrated circuitry. The bond-pads, for example, can include a reference voltage (Vref) bond-pad and a signal bond-pad adjacent to the Vref bond-pad. The signal bond-pad can be for a clock signal, a data signal, a strobe signal, an address signal, or another type signal for operating the integrated circuitry. The support structure can be a lead frame or a interposing substrate having a plurality of conductive members coupled to the bond-pads of the die. The conductive members can accordingly be metal pins in the case of lead frames or traces and solder ball-pads in the case of interposing substrates.

Abstract: Microelectronic devices having a protected input and methods for manufacturing such microelectronic devices. A microelectronic device has a microelectronic die and a support structure for coupling the die to voltage and signal sources. The microelectronic die can have integrated circuitry and a plurality of bond-pads coupled to the integrated circuitry. The bond-pads, for example, can include a reference voltage (Vref) bond-pad and a signal bond-pad adjacent to the Vref bond-pad. The signal bond-pad can be for a clock signal, a data signal, a strobe signal, an address signal, or another type signal for operating the integrated circuitry. The support structure can be a lead frame or a interposing substrate having a plurality of conductive members coupled to the bond-pads of the die. The conductive members can accordingly be metal pins in the case of lead frames or traces and solder ball-pads in the case of interposing substrates.

Abstract: Microelectronic devices having a protected input and methods for manufacturing such microelectronic devices. A microelectronic device has a microelectronic die and a support structure for coupling the die to voltage and signal sources. The microelectronic die can have integrated circuitry and a plurality of bond-pads coupled to the integrated circuitry. The bond-pads, for example, can include a reference voltage (Vref) bond-pad and a signal bond-pad adjacent to the Vref bond-pad. The signal bond-pad can be for a clock signal, a data signal, a strobe signal, an address signal, or another type signal for operating the integrated circuitry. The support structure can be a lead frame or a interposing substrate having a plurality of conductive members coupled to the bond-pads of the die. The conductive members can accordingly be metal pins in the case of lead frames or traces and solder ball-pads in the case of interposing substrates.

Abstract: A method and apparatus for delivering electrical power to a semiconductor die is provided in which a metal frame (104) is applied to the top surface of a semiconductor die. The metal frame include two voltages leads (106, 108), each adjacent to each series of bond pads (116) formed on the top surface of the Semiconductor die. Each voltage lead includes a longitudinal portion (122) adjacent bond pads (116) in the center of the semiconductor die and corner portions (124) or arm portions (125) adjacent bond pads (116) located in the quadrants (114) of the semiconductor die.

Abstract: A method and apparatus for delivering electrical power to a semiconductor die is provided in which a metal frame (104) is applied to the top surface of a semiconductor die. The metal frame include two voltages leads (106, 108), each adjacent to each series of bond pads (116) formed on the top surface of the semiconductor die. Each voltage lead includes a longitudinal portion (122) adjacent bond pads (116) in the center of the semiconductor die and corner portions (124) or arm portions (125) adjacent bond pads (116) located in the quadrants (114) of the semiconductor die.

Abstract: A method and apparatus for delivering electrical power to a semiconductor die is provided in which a metal frame (104) is applied to the top surface of a semiconductor die. The metal frame include two voltages leads (106, 108), each adjacent to each series of bond pads (116) formed on the top surface of the semiconductor die. Each voltage lead includes a longitudinal portion (122) adjacent bond pads (116) in the center of the semiconductor die and corner portions (124) or arm portions (125) adjacent bond pads (116) located in the quadrants (114) of the semiconductor die.

Abstract: In a surface mount assembly, an active integrated circuit device, such as, for example, a dynamic random access memory, typically has a lead finger attached to a solder pad of a printed wiring board. The surface mount assembly is significantly improved by configuring a passive component, such as a resistor or capacitor, such that it has metallic terminations on an upper and lower surface so that it may be positioned between the solder pad of the printed wiring board and the lead finger.

Abstract: The invention discloses a high density semiconductor package. Two semiconductor chips are each affixed on a corresponding one of two lead frames. The semiconductor chips and the lead frames are encapsulated, wherein only a portion of the leads of the lead frames protrudes and extends from the package.

Abstract: The invention discloses a semiconductor package having two rows of interdigitated leads. The two rows of leads (14, 16) are affixed on and extend from one side of the semiconductor package (10). The two rows of leads (14, 16) are interdigitated with each other in a non-contacting manner. The end portions of the leads (17) are further shaped to form a contact surface for soldering to electrical conductors on a printed circuit board.

Abstract: A hybrid leadframe-over-chip (LOC) semiconductor package is generally comprised of bonding finger elements located over a surface of a semiconductor component and electrically coupled, by means of conducting wires, to the bonding pads located on the surface. In addition, at least one bonding finger is located outside the boundary of the surface of the semiconductor component. Each bonding finger located outside the boundary is coupled, by a conducting wire, to a bonding pad positioned within the boundary of the semiconductor component. In this manner, for a given semiconductor component size and for given routing and lead dimension constraints, a larger number of conducting paths can be provided between the leadframe and the semiconductor component.

Abstract: A hybrid leadframe-over-chip (LOC) semiconductor package is generally comprised of bonding finger elements located over a surface of a semiconductor component and electrically coupled, by means of conducting wires, to the bonding pads located on the surface. In addition, at least one bonding finger is located outside the boundary of the surface of the semiconductor component. Each bonding finger located outside the boundary is coupled, by a conducting wire, to a bonding pad positioned within the boundary of the semiconductor component. In this manner, for a given semiconductor component size and for given routing and lead dimension constraints, a larger number of conducting paths can be provided between the leadframe and the semiconductor component.

Abstract: The present invention provides a modular electronic component (10) wherein a sequence: of leads (26) of a lead frame (12) differs from a sequence of bonding pads (16) on an integrated circuit (14). When lead frame (12) is placed adjacent integrated circuit (14), first and second power buses (22) and (24) are disposed on a first side (18) of bonding pads (16). First portion (30) of leads (26) and lead finger (28) are disposed on second side (20) of bonding pads (16). Bonding members (42) couple appropriate bonding pads (16) with corresponding leads (26), first and second power buses (22) and (24), and lead finger (28). In this manner, the pin out of modular electronic component (10) may be altered by incorporating appropriate lead fingers (28) without changing the sequence of bonding pads (16).

Abstract: In a lead on chip, LOC, integrated circuit packaging arrangement, the conductors terminate in fingers that receive the bond wires. Adjacent the fingers, the conductors have arm parts extending over the major face of the integrated circuit. These arm parts are formed by stamping, rolling or otherwise to present an upwardly opening channel with at least the bottom lateral margins of the arm part raised above the plane of the bottom surface of the arm part. This reduces sagging of the arm part and capacitive interaction with the integrated circuit.

Abstract: The invention discloses a high density semiconductor package. In one embodiment, two semiconductor chips are each affixed on a corresponding one of two lead frames. The semiconductor chips and the lead frames are encapsulated, wherein only a portion of the leads of the lead frames protrudes and extends from the package.

Abstract: A process for manufacturing a semiconductor package having two rows of interdigitated leads. The two rows of leads (14, 16) are affixed on and extend from one side of the semiconductor package (10). The two rows of leads (14, 16) are interdigitated with each other in a non-contacting manner. The end portions of the leads (17) are further shaped to form a contact surface for soldering to electrical conductors on a printed circuit board.

Abstract: The present invention provides a modular electronic component (10) wherein a sequence of leads (26) of a lead frame (12) differs from a sequence of bonding pads (16) on an integrated circuit (14). When lead frame (12) is placed adjacent integrated circuit (14), first and second power buses (22) and (24) are disposed on a first side (18) of bonding pads (16). First portion (30) of leads (26) and lead finger (28) are disposed on second side (20) of bonding pads (16). Bonding members (42) couple appropriate bonding pads (16) with corresponding leads (26), first and second power buses (22) and (24), and lead finger (28). In this manner, the pin out of modular electronic component (10) may be altered by incorporating appropriate lead fingers (28) without changing the sequence of bonding pads (16).

Abstract: A flat package for semiconductor integrated circuit devices allows edge-mounting and surface-mount. The package may be molded plastic containing a semiconductor chip, and flat leads extend from one edge of the package. The leads are bent to provide an area to solder to conductors on a PC board. Mechanical positioning, mechanical support and spacing are provided by studs extending from the edge of the package adjacent the leads. The studs have stops formed at a position even with flat outer surfaces of the bent leads; the portion outward of the stops fits into holes in the PC board.

Abstract: A flat package for semiconductor integrated circuit devices allows edge-mounting and surface-mount. The package may be molded plastic containing a semiconductor chip, and flat leads extend from one edge of the package. The leads are bent to provide an area to solder to conductors on a PC board. Mechanical positioning, mechanical support and spacing are provided by studs extending from the edge of the package adjacent the leads. The studs have stops formed at a position even with flat outer surfaces of the bent leads; the portion outward of the stops fits into holes in the PC board.

Abstract: A ceramic semiconductor package has a ceramic bridge to provide shorter bond wire lengths and other interconnections for the semiconductor device.

Abstract: A flat package for semiconductor integrated circuit devices allows edge-mounting and surface-mount. The package may be molded plastic containing a semiconductor chip, and flat leads extend from one edge of the package. The leads are bent to provide an area to solder to conductors on a PC board. Mechanical positioning, mechanical support and spacing are provided by studs extending from the edge of the package adjacent the leads. The studs have stops formed at a position even with flat outer surfaces of the bent leads; the portion outward of the stops fits into holes in the PC board.